I have a PLL that tracks the phase lag of a resonance system. When unwrapped, my system's phase lag has values beyond $-\pi$ to $\pi$.

After unwrapping phase lag, are there any bounds on the phase difference between signals? I assumed that the bounds were always from $-\pi$ to $\pi$ since a phase difference greater than $\pi$ could be expressed as a negative difference between $-\pi$ and $0$.

x-axes should say "Frequency"



  • $\begingroup$ What are you trying to do? $\endgroup$
    – Ben
    Feb 22 at 17:24
  • $\begingroup$ @Ben I have an FPGA-based PLL with a lock-in amplifier (LIA) phase detector. This system outputs a sine wave from a DAC and reads a sine wave into the ADC. The signal outputted from the DAC drives a tuning fork, and this tuning fork outputs a current that is later converted to a voltage that is read into the ADC. My LIA calculates the phase difference between the ADC and DAC signals. This phase difference is shown above $\endgroup$ Feb 22 at 18:27
  • $\begingroup$ Short answer, yes it can. The missed "periods" won't be noticed by your PLL. $\endgroup$
    – Ben
    Feb 22 at 18:35
  • $\begingroup$ They key is how you feed the phase to your PLL. If the phase fed to your PLL is bound between $±\pi$, then the PLL will try to set the phase difference between the input and its output to 0, nothing more, nothing less. So it is possible that the PLL will have missed a few cycles. Or maybe your PLL will lead your input by a number of cycles. However, if you unwrap the phase at the input of your PLL, then number of cycles should be the same. $\endgroup$
    – Ben
    Feb 22 at 19:09

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