I am programming a phase-locked loop to track the resonance of a tuning fork so that the tuning fork is always on resonance. This will be used in condensed matter physics through atomic force microscopy.
Now, I am not certain about how to carry this out, so I was wondering if someone here could help me.
I have programmed an FPGA to output an arbitrary driving voltage, and this drives a tuning fork. This tuning fork then generates a signal that is eventually converted to a voltage and read by my device. Now, I also have a lock-in amplifier to detect the phase lag between my DAC (technically, the NCO that outputs via DAC) and ADC signals. I have made a graph of the phase difference after taking 4000 steps around the resonance frequency. Also, there is a graph of the LIA's detected magnitude*2.
I do not know what any of the transfer functions are, I apologize.
Phase difference (phase lag) graph on left. Resonance centered at 32.7635 kHz However, my phase difference graph is likely incorrect. I found the following that displays continuous "pretty" graph that may be what I am supposed to have.
Phase lag in blue
Does anyone know why phase graph has a max/min of 1/-1? If so, does anyone know how I may fix it?