My question is related to the quantization error and the functionality of SAR-ADCs. In general, the quantization error of an ADC is defined as +-0.5LSB. If this concept is correct a voltage that equals 1.75LSB, would produce 2LSB at the output of the ADC and a voltage that equals 1.25LSB would produce 1LSB at the output of the ADC. Based on the linked example transformation curve we got
U_LSB = 1V/(2^3bit) = 0,125V, so an input voltage of 0,21875V (1.75LSB) would produce an output voltage of 0,250V and an input voltage of 0,15625V would produce an output voltage of 0,125V. So far so good. Let’s jump to the basic concept of an SAR-ADC.
An input voltage Vin is sampled by a sample-and-hold block. This sampled voltage is then compared by a comparator with a known voltage. This known voltage V_DAC is provided by the DAC that is supplied by a reference voltage Vref. The digital input for the DAC is generated by a SAR register as a digital word. This digital word depends on the result from the comparator. Initially the SAR begins with setting the MSB. After that the output voltage V_DAC of the ADC is compared with the input voltage Vin. If Vin is greater than V_DAC the MSB stays set. If Vin is less than V_DAC the MSB will be set to zero again. In the next step the SAR register sets the following bit and the comparison process of V_DAC and Vin goes on, until the LSB is reached.
My problem lies in this strict comparison process, which will never allow the output voltage of the ADC to be higher than the input voltage Vin. When I take the example from the first paragraph a SAR-ADC would give me 0,125V (1LSB) as an output voltage, as long as I don’t exceed 0,250V (2LSB). So an input voltage of 1.25LSB and 1.75LSB would both provide 1LSB output. This would mean the concept of +-0.5LSB quantization error wouldn’t be correct for SAR-ADCs and the ideal transformation steps would be shifted to the right for like 0.5ULSB (see diagram with red curve). The new quantization error would be max. -1LSB.
Is this thinking process correct or am I missing something? I can’t imagine that the general concept of quantization error does not match with the architecture of SAR-ADCs…