Say we have a 12-bit ADC with 30 MHz sampling frequency. I want to perform several DSP operations on output digital signal so that resulting signal would have increased accuracy to 14 bits and output sampling frequency would become 2 MHz. In nutshell I want a DSP block that converts a 12-bit ADC with 30 MHz Sampling rate to a 14-bit ADC with 2 MHz sampling. Even a slight tip for me to know where to look for would be helpful. (This project would be implemented on a FPGA.)
With typical sampling (not noise shaped) you get half a bit for every halving of the sampling rate (with proper filtering of the out of band noise prior to downsampling). So a decimate by two for example consists of a half band filter followed by a down-sample by two which is done simply by selecting every other sample. Assuming white noise, the half band filter removed half the noise or 3 dB, and the the SNR of ADC’s goes as 6 dB/bit.
Therefore, if you went from 30 MHz to 7.5 MHz with a decimate by four, you would gain a full bit or 12 bits extended to 13 bits assuming noise is limited by quantization noise and the quantization noise process is sufficiently white as typically assumed and approximated.
It’s should be straight forward to see now how to go from 12 bits to 14 bits through successive decimations. (And the filtering and decimation can be done in one block each or distributed which gives flexibility in the filter designs used).
An additional caution when working with real hardware is to refer to the expected Effective Number of Bits (ENOB) for the actual ADC used and in what conditions of sampling, input frequency etc as the number of bits to be achieved and improved on, and pay attention to actual spur levels (as given by the Spurious Free Dynamic Range, SFDR) that will ultimately limit the SNR since decimation will do nothing to reduce the power level of in band spurs. Often these spurs are below the noise level due to quantization in which case dynamic range improvement can be gained through decimation.