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I'm trying to design a low pass filter in Verilog for use on a Red Pitaya's FPGA (Xilinx® Zynq®-7010).

All I'm trying to get the low pass filter to do is to obtain the DC component in the signal.

The only part of the signal I require is the DC component.

Can someone put me through on how to go about the design as I am new with Red Pitaya?

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There are 2 steps for the solution

Step 1 - Design some kind of low-pass filter to measure the DC component.

In order to perform step 1 you need to answer a few questions :

What do you mean by DC? For example, measure the DC for the last 10 seconds?

What is the input sampling rate? What is the desired output sampling rate?

You need to provide this information, we cannot guess it for you.

Step 2 - Implement the filter in Verilog.

There are examples on opencores. I can also give you a hand if you need help with implementing a FIR or IIR filter in Verilog.

You could also look at the Xilinx FIR Cores in the Core generator.

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  • $\begingroup$ Thanks so much for your response. I'm trying implement a measuring system that can measure DC current on real time in power transformer neutrals. The input analog signal will contain up to 60th harmonic, so I feel the sampling rate for the ADC should be 6KHz. The digital low pass filter I'm trying to implement is an FIR filter with a cut off frequency of 0.66Hz. I really need help in implementing this FIR filter as I am new with redpitaya and verilog. Thanks $\endgroup$ – Llanre Sep 6 at 0:05

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