It depends, but convolutional codes like these are usually decoded using maximum likelihood sequence estimation, typically through the Viterbi decoder.
The design methodology for any decoder doesn't start with an electronics implementation of the encoder (that is something that's highly specific to the speed and technology you want to use), but with a general design of the encoder, usually in shape of the polynomial that your circuitry implements.
Draw the state diagram to the encoder, then draw the trellis diagram to that, and then you gain something you can implement as viterbi decoder.
I can't see a case where someone would ever actually implement this encoder using discrete 74xx series logic gates like you do – I presume this is just a representation of the logic.
You can implement encoding logic very easily in software, running on a microcontroller; if you need 100s of megabits per second in throughput, you'd implement this in an FPGA, but then, this encoder wouldn't, from a code design point of view, be what you use to begin with, probably. So, sure, this is also something you can easily implement using logic gates.
Decoding is always more complex than encoding. Decoding convolutional codes is kind of inherently something that you'll need to test hypotheses while doing; this will be no fun / make no sense to implement in discrete logic components (gets way too large, and thus, too bug-prone very quickly), you'd do that in software, really, or on an FPGA.
Just like for your previous question: you can't understand how this works by implementing it in hardware first without reading any theory. So, wikipedia: convolutional codes, Trellis diagram, Viterbi decoder.