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Im struggling to implement / build convolutional decoder . I've done implementation of FEC encoder which it's as shown in the photo below: enter image description here

So this is the encoder that I've implemented, and I want to do for it the decoder, from where could I start and how can I implement for this encoder the decoder? (decoder is working opposite to encoder and I know that but from where do I start and how to implement that decoder as what I did in my encoder photo)

thanks for any help/assistance.

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It depends, but convolutional codes like these are usually decoded using maximum likelihood sequence estimation, typically through the Viterbi decoder.

The design methodology for any decoder doesn't start with an electronics implementation of the encoder (that is something that's highly specific to the speed and technology you want to use), but with a general design of the encoder, usually in shape of the polynomial that your circuitry implements.

Draw the state diagram to the encoder, then draw the trellis diagram to that, and then you gain something you can implement as viterbi decoder.

I can't see a case where someone would ever actually implement this encoder using discrete 74xx series logic gates like you do – I presume this is just a representation of the logic.

You can implement encoding logic very easily in software, running on a microcontroller; if you need 100s of megabits per second in throughput, you'd implement this in an FPGA, but then, this encoder wouldn't, from a code design point of view, be what you use to begin with, probably. So, sure, this is also something you can easily implement using logic gates.

Decoding is always more complex than encoding. Decoding convolutional codes is kind of inherently something that you'll need to test hypotheses while doing; this will be no fun / make no sense to implement in discrete logic components (gets way too large, and thus, too bug-prone very quickly), you'd do that in software, really, or on an FPGA.

Just like for your previous question: you can't understand how this works by implementing it in hardware first without reading any theory. So, wikipedia: convolutional codes, Trellis diagram, Viterbi decoder.

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  • $\begingroup$ Thanks ! here the state machine is very long it's 2^(6) states ! and for every state need to determine what happened for D=1 or D=0 ..it's too long state machine , isn't there another approach to implement the decoder? what Im working on? Im working on reciever that receive packets, on the transmitted side there's convolutional fec encoder, so in the receiver side I want to implement the fec decoder .. $\endgroup$ Aug 25 '20 at 14:25
  • $\begingroup$ if I want to do the code of fec decoder on software, Im still stuck from where to start, lets say I want to do fec decoder in c from where to start $\endgroup$ Aug 25 '20 at 14:47
  • $\begingroup$ I've read about decoder (Viterbi algorithm) ..almost understand all but didn't understand when I use hamming distance, what if there was two branches with the same weight, which one should I consider?! I mean two branches with the same hamming distance, what should I take? in general I take the min hamming distance value for the branches .. $\endgroup$ Aug 25 '20 at 21:28
  • $\begingroup$ @DavidJohnsons frankly, yes, 64 states is quite a few. You don't need to draw the trellis by hand, you can do it all in software, but then again, your flipflop representation of the encoder doesn't help much, you want the poylnomial. $\endgroup$ Aug 26 '20 at 7:50
  • $\begingroup$ Re: Paths with equal weight: choose one of them randomly. That happens rarely, and all are equally likely to be right. $\endgroup$ Aug 26 '20 at 7:51

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