I am trying to implement a 4th order direct form type II IIR filter in VHDL(Specifically, in xilinx FPGA) and when i implement it i get correct output yet very low maximum clock rate(Around 80 Mhz). So i wanted to know what is the best way to implement IIR filters in terms of speed?Or at least where can i read more about IIR filter implementations in VHDL?

  • $\begingroup$ Can you show your code? $\endgroup$
    – Juha P
    Aug 10 '20 at 11:49

I faced the same problem in the past, the problem is that it's not possible to pipeline the IIR feedback loop without changing the filter equation.

There's one technique you can use, it's called "scattered-look ahead IIR filter"

The gist of it is to change $H(z) = \frac{b_0 + b_1z^{-1} + b_2z^{-2}}{1 + a_1z^{-1} + a_2z^{-2}}$

To this

$H_1(z) = \frac{d_0 + d_1z^{-1} + d_2z^{-2}+d_3z^{-3}+d_4z^{-4}}{1 + c_2z^{-2}+c_4z^{-4}} = H(z)$

since the odd feedback coefficients are 0, it is possible to use pipelining in the feedback loop thus increasing the maximum frequency.

To go from $H(z)$ to $H_1(z)$ ou need to factor $$H(z) = \frac{b_0 + b_1z^{-1} + b_2z^{-2}}{1 + a_1z^{-1} + a_2z^{-2}} = \frac{b_0 + b_1z^{-1} + b_2z^{-2}}{1 -2rcos(\theta)z^{-1} + r^2z^{-2}} $$

$$H(z) = \frac{b_0 + b_1z^{-1} + b_2z^{-2}}{1 -2rcos(\theta)z^{-1} + r^2z^{-2}} * \frac{re^{±(j(\theta+\pi/2))}}{re^{±(j(\theta+\pi/2))}} = \frac{d_0 + d_1z^{-1} + d_2z^{-2}+d_3z^{-3}+d_4z^{-4}}{1 + c_2z^{-2}+c_4z^{-4}}$$

Edit :

If your poles are not complex, the technique I showed will not work. However you can still apply the look-ahead. You simply need to transform the order-2 filter in 2 cascaded order1- filters and then apply the lookahead transform.

You should consult this site for more information http://people.ece.umn.edu/users/parhi/SLIDES/chap10.pdf

  • $\begingroup$ Thanks a lot...would you please provide an example? $\endgroup$
    – Krsh
    Aug 11 '20 at 5:19
  • $\begingroup$ I might have time later this week. $\endgroup$
    – Ben
    Aug 11 '20 at 13:17

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