My bitrate clock will have an instantaneous period of 32 or 40 ns (but a mean of 32.26ns)
That won't work great. I'd hardly call a 20% too long period "jitter", anymore. You're simply not synthesizing a useful clock; you're average correct rate doesn't help a receiver much to get a lock on your symbol timing.
The "easy" solution is use the facilities of your FPGA to actually produce a 31 MHz clock.
If there's no clock synthesizer that can do that for you: You'll have to resample your signal internally. There's no need that your sample rate needs to be a multiple of your symbol rate, it's just easy to deal with.
But really, you can calculate what your transmit signal would look like at any rate (e.g. sampled at 62 MS/s) and then resample it to a rate that your system actually works at (e.g. 62.5 MS/s). There's no need for an actual 15.5 MHz clock to generate a baseband signal at 15.5 Msym/s QPSK to transport your 31 Mbit/s.
So, what you need is a rational resampler with a rate of 125/31 or 250/31 or so.
Your FPGA vendor quite likely has an IP core for that. If not, it's no magic, but will take some development time. You're looking for a polyphase implementation of a rational resampler if you need to implement that yourself, so that you can first decimate your signal by 31 and then interpolate by 125 (or 250, or so).