I have a question regarding an implementation of a modulator.

I guess some people here have an FPGA background.

I would like to implement a QPSK modulator of  31 Mbit bitrate using a 125 MHz clock. I plan to generate the bitrate clock using MSB with a 32 bit phase accumulator also what can be called an NCO.

A 125 MHz clock has a 8 ns period. A 31 MHz bit clock has a 32.26 ns period. My bitrate clock will have an instantaneous period of 32 or 40 ns (but a mean of 32.26ns)

Is this a big issue to generate that kind of jitter on a modulator? Is there a performance impact on a receiver? Or maybe there is an another way implementing this?



My bitrate clock will have an instantaneous period of 32 or 40 ns (but a mean of 32.26ns)

That won't work great. I'd hardly call a 20% too long period "jitter", anymore. You're simply not synthesizing a useful clock; you're average correct rate doesn't help a receiver much to get a lock on your symbol timing.

The "easy" solution is use the facilities of your FPGA to actually produce a 31 MHz clock.

If there's no clock synthesizer that can do that for you: You'll have to resample your signal internally. There's no need that your sample rate needs to be a multiple of your symbol rate, it's just easy to deal with.

But really, you can calculate what your transmit signal would look like at any rate (e.g. sampled at 62 MS/s) and then resample it to a rate that your system actually works at (e.g. 62.5 MS/s). There's no need for an actual 15.5 MHz clock to generate a baseband signal at 15.5 Msym/s QPSK to transport your 31 Mbit/s.

So, what you need is a rational resampler with a rate of 125/31 or 250/31 or so.

Your FPGA vendor quite likely has an IP core for that. If not, it's no magic, but will take some development time. You're looking for a polyphase implementation of a rational resampler if you need to implement that yourself, so that you can first decimate your signal by 31 and then interpolate by 125 (or 250, or so).

  • $\begingroup$ Generating a pure 31 MHz from FPGA PLL is not the best choice for me as I would like to cover more bitrates $\endgroup$ – gotchi85 Jul 17 '20 at 20:35
  • $\begingroup$ I plan to use an RRC filter at 62 Msps after zero padding then upsampling through a polyphase to 125 Msps as you suggest. But the mapped QPSK symbols will have a jitter inside from the 15.5 Msps not being clean... $\endgroup$ – gotchi85 Jul 17 '20 at 20:39
  • $\begingroup$ That makes no sense? You're confusing data rate and clock rate, somehow, and why the RRC should run at yet another rate is really confusing... $\endgroup$ – Marcus Müller Jul 17 '20 at 23:00
  • $\begingroup$ Why do I confuse data rate and clock rate? $\endgroup$ – gotchi85 Jul 18 '20 at 8:33
  • $\begingroup$ Using an RRC filter at four samples per symbol instead of two is not strange for me. However, this solution may have a jitter on data if we look at the eye diagram of the result (oversampled). That is my main question. Thanks $\endgroup$ – gotchi85 Jul 18 '20 at 8:37

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