# How does the world's simplest sigma-delta DAC work?

I have run into a simple delta-sigma (supposedly, where is the delta part?) DAC implementation utilizing an accumulator and then using the overflow bit as a modulated 1-bit output.

module PWM(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output PWM_out;

reg [8:0] PWM_accumulator;
always @(posedge clk) PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;

assign PWM_out = PWM_accumulator[8];
endmodule


I have implemented this and tested on an FPGA and compared it to a delta-sigma DAC from Xilinx app note: https://www.xilinx.com/support/documentation/application_notes/xapp154.pdf

module ds_modulator (
output DACout,
input [7:0] DACin,
input Clk,
input Resetn
);

reg DACout;
reg [9:0] SigmaLatch;
reg [9:0] DeltaB;

assign DeltaB = {SigmaLatch[9], SigmaLatch[9], 8'b0};
assign DeltaAdder = DACin + DeltaB;

always @(posedge Clk, negedge Resetn) begin
if (!Resetn) begin
SigmaLatch <= 10'b1111111111;
DACout <= 1'b0;
end else begin
DACout <= SigmaLatch[9];
end
end

endmodule


I am looking for as simple as possible delta-sigma DAC containing minimum logic while still maintaining reasonable performance. The very simple accumulator-overflow solution seems to work great. I understand it conceptually--high values will cause more frequent overflows and low values will cause less frequent overflows. Are there any disadvantages? I am using 120 MHz sampling frequency and generating sine waves between 100 kHz and 500 kHz through direct digital synthesis.

I am interested in this simple approach. Can someone shine light on why it works so well while being so simple? Also, if there is an official name for this approach or if there is some analysis somewhere online, it would be greatly appreciated if you can reference it in your reply.

I also found the simple accumulator-overflow DAC reference here (page 71): https://github.com/hamsternz/IntroToSpartanFPGABook/blob/master/IntroToSpartanFPGABook.pdf

Thank you.