I know that DSPs are specialized processors but i want to know what will happen if DSPs are replaced by general purpose processor in their applications? I know one application,mobile phone,will that work normally if DSP of mobile is replaced by a normal(general purpose microprocessor)

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    $\begingroup$ slower, more expensive, or both. $\endgroup$
    – AlexTP
    Jul 4, 2020 at 20:22
  • $\begingroup$ Someone will have to write different software for the different processor. You can't just desolder the DSP and solder a non-DSP microprocessor and expect it to work. $\endgroup$ Jul 4, 2020 at 23:47
  • $\begingroup$ Old slides - bdti.com/MyBDTI/pubs/050307ESC_MPUs_vs_DSPs.pdf . $\endgroup$
    – Juha P
    Jul 5, 2020 at 5:37
  • $\begingroup$ By your last line,you mean,dsp processor will lose their worth in near future and will be replaced by general purpose processor in all their applications? $\endgroup$
    – DSP_CS
    Jul 5, 2020 at 7:08
  • $\begingroup$ FourierFlux, this is pretty nonsense ranting, not an answer. DSP ICs are highly optimized things that allow engineers to do things that would be impractical with general-purpose CPUs and FPGAs. They're simply something different. Yes, a larger share of what they excelled at is now solved with FPGAs. That doesn't make them shitty. No, in the future not everything will be done with Neural Compute hardware. That literally makes no sense - we have plenty of algorithms that are provably optimal, i.e. no neural net could ever be better,and that aren't sensibly computable on "neural compute hardware" $\endgroup$ Jul 5, 2020 at 10:08

1 Answer 1


On a basic level, in my opinion, a DSP chip must, as a minimum requirement, be able to optimally perform the convolution summation used to compute the output of an FIR filter.

$$ y[n] = \sum\limits_{k=0}^{K-1} h[k] \, x[n-k] $$

$y[n]$ = FIR filter output

$x[n]$ = FIR filter input

$h[k]$ = impulse response of FIR filter (also FIR coefficients)

To do this in $K$ instructions, one must be able to in one instruction:

  1. Do a multiplication and addition, implemented as a single multiply-accumulate (MAC) instruction.

  2. Fetch both the delayed sample, $x[n-k]$ and the FIR coefficient $h[k]$ for the next MAC. To do both, this requires at least two data memory spaces: one for coefficient array $h[k]$, one for the signal array $x[n]$. Both spaces can be accessed in parallel (simultaneously). This is called a "Harvard Architecture".

  3. Be able to saturate the results to defined maximum positive or negative values if the result exceeds that range.

  4. Besides being able to saturate to the "rails", the Arithmetic Logic Unit (ALU) in the DSP should be able to round to the nearest LSB of the high-order bits (that will be output or saved to memory) based on the low-order bits of the accumulator.

  5. To address the delayed samples in memory, the ability to do modulo arithmetic on the pointer to $x[n-k]$ is necessary. This implements a "circular queue" or "circular buffer" or "first-in-first-out" (FIFO) buffer which, in the audio DSP world, is just called a "delay line". The DSP programmer should not have to worry about when a pointer increments beyond the boundary of a circular queue requiring the pointer to be adjusted or wrapped around. The DSP chip should make that modulo adjustment to the pointer automatically.

  6. In addition, for the FFT, the ability to do bit reversal or bit-reversed addressing is necessary along with some other handy instructions that make for efficient coding of FFT butterflies.

Now, in order to be a "DSP chip", it really should be able to do all of these operations without explicit instructions in the inner loops. They build it into the hardware of the ALU the means to perform those operations without explicit effort from the programmer (nor extra machine instruction cycles). Nothing prevents you from using a normal CPU to do all of these operations, even in a "high-level" language like C/C++ . And the general purpose CPU chip might be running at 5 GHz while the DSP chip is running at 500 MHz, so the 10x instruction speed might more than make up for the cost of all those extra instructions that the algorithm programmer must code.

  • $\begingroup$ Importantly, extended precision accumulators! $\endgroup$ Jul 5, 2020 at 0:11
  • $\begingroup$ I'll admit I copied much of the text above from my comp.dsp post from 24 years ago and that was one of the items. but it's more of an issue with fixed-point and there are DSPs such as SHArCs that kinda half-way extend the precision for floating-point (40-bit float registers). i didn't want to make the answer fixed-point centric. $\endgroup$ Jul 5, 2020 at 2:01
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    $\begingroup$ Good answer overall; I upvoted it! $\endgroup$ Jul 5, 2020 at 2:02
  • $\begingroup$ thank you, Dan. $\endgroup$ Jul 5, 2020 at 2:06
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    $\begingroup$ Concluding from your last paragraph: " There isn't apparently much difference between both cases in terms of performance/speed but in case of normal(general purpose microprocessor) ,extra code lines need to be introduced to balance the hardware benefits of dsp? $\endgroup$
    – DSP_CS
    Jul 5, 2020 at 7:07

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