# Hilbert Transform on split datastream produces phase flip

this is my first post here!

I'm trying to do phase correction on a signal from a linear CCD (2048 pixels, 10bit per pixel, 250kHz linerate) in an FPGA. Therfore I need to generate an analytical signal from the real sensor data. The sensor outputs 8 pixels in parallel to achieve the high datarate of 512 megapixels per second.

The signal is first k-linearized and normalized and then fed into a real FFT, the imaginary part is set to zero. As a tradeoff between speed and resources I buffer the datastream and perform the FFT on 4 parallel channels at double speed. The first channel gets the 0th,4th,8th pixel, the second channel the 1st,5th,9th pixel, etc.

Then the upper half of each spectrum is then zeroed and an inverse FFT is performed. The 4 resulting analytic signal channels are then combined according to the algorithm from this page (https://www.dsprelated.com/showarticle/63.php).

This all works fine if the main frequency of the original signal lies between 0 and 256 or between 513 and 768. But when the frequency is 257-512 or 769-1024 the phase flips by 180° (the imaginary part has the opposite sign). These numbers correspond to the size of the four segments (256 pixels per segment.)

This doesn't happen when the same calculation is done with only one channel. But due to speed and resource constraints, the FFTs have to be parallelized.

Is there any way to prevent this?

Unfortunately, I don't have much experience with the mathematical side of things, I just convert C algorithms into parallelized, pipelined FPGA code. But I have built the whole processing in Matlab and verified the problem is not just a bug in the VHDL implementation.

I'd be grateful for any input you might have! Thanks!

• Can you reproduce this problem in Matlab? It would help determine whether it's an FPGA problem or an algorithm problem (in your case multiplexing pixels)
– Ben
Jun 9 '20 at 20:57
• I reproduced the problem in Matlab. It shows the same behavior as the FPGA. Jun 9 '20 at 21:31
• Perhaps you should rephrase your question as it is not FPGA-specific.
– Ben
Jun 10 '20 at 13:30