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PLL is typically used in carrier synchronization and its diagram is well known, consisting of a multiplier, a low pass filter, and a VCO.

In "Phase-locked Loop" at wiki (https://en.wikipedia.org/wiki/Phase-locked_loop), it says in the "Application" section that PLL can be used for symbol synchronization. Does anybody have a standard diagram for this application, with some analysis on how it works?

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  • $\begingroup$ Google "bit timing recovery". $\endgroup$
    – TimWescott
    Commented May 29, 2020 at 20:54
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    $\begingroup$ A textbook by Rice or Mengali should have a thorough explanation. But if you want a short explanation there's this: gnuradio.org/grcon/grcon17/presentations/… .The PLL is estimating and tracking the symbol clock period and symbol clock timing offset (aka symbol clock phase). The symbol clock is a hidden quantity that has to be estimated from the incoming data symbols using a timing error detector. $\endgroup$
    – Andy Walls
    Commented May 30, 2020 at 2:17
  • $\begingroup$ "No. it is a different concept." Bits aren't symbols? Wow. I never knew. $\endgroup$
    – TimWescott
    Commented May 30, 2020 at 3:25
  • $\begingroup$ Andy: I think the key part in your scheme should be the TED (timing error detector). The rest is easy. Can you briefly explain the algorithm you used for the design of this TED component? I think you have presented the answer for my question. Thank you. $\endgroup$
    – Cindy
    Commented May 30, 2020 at 23:31

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