I have read many of the articles on the website regarding a polyphase decimating filter structure. I'm sure we are all familiar with the typical image shown in Fred Harris Multirate book and many other papers written on this topic below.
Say we have some transfer function H(z).. well the polyphase implementation works by decimating the filter into M parallel filters where fs/M is the desired output rate. The noble identities tell us we can pull the decimation through the filter stages... and hence the delays at the input are replaced by the commutator switch which effectively sends samples in at rate fs/M. Let N be the total number of taps in H(z)... the convenience of this is that we only need to filter with N/M taps per cycle which greatly reduces resources... ok I've done my homework.
Now my question. I have seen many implementations of this structure in code but I can't seem to find any implementations in simulink...specifically with what exactly is the commutator switch?
Here is an implementation that I have created in simulink... although it clearly doesn't work properly...Say I have some filter that was originally 120 taps and I now want an output rate that is 1/4 of the input rate... I decimate my filter into 4 sub filters and arrange into a parallel structure as shown below:
The switch on the input has a counter attached to it because I'm thinking that I can cycle between inputs at each clock edge to simulate the commutator...but then I need to demux the data into a branch that I want.. however this isn't working because the demux isn't controllable...
What am I doing wrong here? What is the block that simulates the commutator like shown in many of the block diagrams in the multirate papers we all know? I realize that it's a memoryless switch but which simulink block ?