# What does an ADC DNL specification mean, exactly?

I'm looking at the differential non-linearity specification for an Analog-Digital converter. The spec sheet claims that the DNL ranges from -1LSB to +1LSB, with a typical value of $$\pm$$0.6LSB. What exactly does that mean? Is this some value that's taken statistically? Does this mean the 3$$\sigma$$ value is 0.6LSB? I.E., for any given code, the range of voltages over which it has jurisdiction is 99.7% likely to be no greater than 1.6LSB or less than 0.4LSB?

Suppose I wanted to model a 16-bit ADC with these specifications. How would I go about injecting DNL into the output codes? The spec sheet is completely unclear as to what 0.6LSB means. Is there some statistical convention? Or would it just be some random number which caps at $$\pm$$1LSB for every single code?

If I was to model this, I was first tempted to generate a Gaussian random sequence with a standard deviation of $$\sigma = (0.6) 4/\pi$$ and clamp it at $$\pm 1$$ since the mean of the absolute value of a Gaussian R.V. Is $$(4/\pi)\sigma$$... but the clamping reduces the mean, so increasing that to $$\sigma = (0.7) 4/\pi$$ results in a random (clamped Gaussian) distribution that never exceeds ±1 but also has an average magnitude (therefore typical) of 0.6.