This is a "DSP Puzzle", Please preface your answer with spoiler notation by typing the following two characters first ">!" as the intention is for readers to think through what the solution might be first (the ones that want to participate, others can hover over immediately to see the solution).
A second order "type 2" Phase Lock Loop is required in order to track a phase ramp with time with zero error. A phase ramp is a frequency step. Similarly a third order "type 3" PLL would be required to track a frequency ramp (phase acceleration), which I have summarized in the graphic below. The "Type" refers to the number of poles in the open loop transfer function at the $s=0$ in continuous time or $z=1$ in discrete time loops, since these represent pure integrators. An integrator has infinite gain at DC and hence infinite suppression of DC error.
A second order type 2 PLL is often implemented with a proportional-integral loop filter, adding the second pole in addition to the oscillator which has an inherent pole since it integrates phase (controlling the output frequency of the oscillator directly is controlling the integral of the phase of the output).
The question is: There is a way to implement a similar tracking system to track a phase ramp with zero error using two first order PLL's. How do we do this?