I'm working on XILINX FFT IP(PG109) in pipeline mode, which uses radix 2 DIF Lattice to perform FFT/IFFT operation. How to perform scaling of each stage in FFT, such that the effect of saturation or underflow will be less?
Input Data: An OFDM Symbol from channel.
My work : 1) Data growth will be due to addition/subtraction and rotation of vector done by twiddle factor.
2) Because of addition/subtraction there will 1 bit growth(when extreme values involves)
FOR DIF ARCHITECTURE BIT GROWTH IN LAST TWO STAGES IS PURELY DUE TO ADDITION/SUBTRACTION AS TWIDDLE VALUES ARE +/-1, +/-j.
3) For rest first N-2 stages, data grows as per note 1 . The max. real/imaginary can go to 2*sqrt(2).
4)Always data growth in every stage can't lead to overflow.(when input values are small).