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I'm working on XILINX FFT IP(PG109) in pipeline mode, which uses radix 2 DIF Lattice to perform FFT/IFFT operation. How to perform scaling of each stage in FFT, such that the effect of saturation or underflow will be less?

Input Data: An OFDM Symbol from channel.

My work : 1) Data growth will be due to addition/subtraction and rotation of vector done by twiddle factor.

2) Because of addition/subtraction there will 1 bit growth(when extreme values involves)

FOR DIF ARCHITECTURE BIT GROWTH IN LAST TWO STAGES IS PURELY DUE TO ADDITION/SUBTRACTION AS TWIDDLE VALUES ARE +/-1, +/-j.

3) For rest first N-2 stages, data grows as per note 1 . The max. real/imaginary can go to 2*sqrt(2).

4)Always data growth in every stage can't lead to overflow.(when input values are small).

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I have worked with 4096-point Radix-2 based FFT algorithms, and although one might think that we need to adjust the accumulation after every stage by rightshifting the accumulation by 1 bit.

But that leads to over scaling of the magnitude and if the input $x[n]$ has low amplitude, then the accumulation at few stages might become 0 after this division by 2.

I found the scaling 0xAAA as most optimal performing one, which means that we are adjusting the accumulation at alternate stage rather than after very stage.

0xAAA : 101010101010 -> Accumulated register is right-shifted by the bit at bit-position in 0xAAA corresponding to the stage.

You can try with 0xFFF also, and actually see that the FFT result is getting higher error at those FFT Coefficients which are having low amplitude.

Hope this helps.

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