Signal Processing Stack Exchange is a question and answer site for practitioners of the art and science of signal, image and video processing. It only takes a minute to sign up.
Sign up to join this community
Referring to "Parallel 1st-order IIR filters" on this wikipedia page, the structure of a 4-parallel IIR filter is discussed. However, the format in which it is implemented seems very odd.
Why is it necessary to iterate the IIR equation N parallel times? Could you not just parallelize it in a direct form. Refer to my chicken-scratch block diagram below.
The main difference between the form the OP is showing and the referenced solution is that the referenced answer isolates the pole and moves it further away from the unit circle resulting in a more stable design applicable to fixed point solutions. In particular the solution the OP gave has delay accumulation from each element that is within the feedback loop (four multiplier and adder elements) which would limit the maximum clock rate that it could operate in a stable condition for in a realizable implementation.
This is depicted in the diagram below showing the synchronous and combinatorial elements. In order for this diagram to accurately match the first order IIR filter (a single feedback tap), the internal functionality shown must be combinatorial. This will run at 1/4 of the clock rate, but will take significantly longer for the state to settle between clock cycles than the implementation shown in the OP's Wikipedia link copied below this image.
OP's Diagram
Wikipedia Diagram (note this is only showing two of 4 outputs ($y[4k]$,$y[4k+4]$), in Ben's answer he links a pdf that shows the expanded version of this on p. 35 that shows all four outputs that would be needed after each clock cycle. In either diagraml this partial one or the complete one, the feedback loop is the same, which is the main point: it consists of only 1 adder and 1 multiplier running at 1/4 the clock rate, rather than 4 adders and 4 multipliers in the critical feedback loop).
The IIR runs at a reduced rate compared to the sample rate.. For example, if the sample rate is 100 MHz, the hardware clock is 25 MHz. That's why the architecture is so weird like you said.
For the record, it is really hard to meet timing closure in an FPGA when the samplingfrequency is higher than 100 MHz because of the combinational delays between the flip-flops (delay elements). There are strategies to work around this problem :
Split your order-2 or order-1 IIR filters in parallel filters and run them at a reduced rate and combine the outputs to get back to your original sample rate.
Or, use a technique like scattered look-ahead to increase the order of your IIR filters, from 2 to 4. Or from 1 to 2. By using clever pole-zero cancellation, you can meet the timing margin more easily. I used this technique in the past.
See http://people.ece.umn.edu/users/parhi/SLIDES/chap10.pdf
In the image below, I explain what causes the combinational delay for a simple IIR order-1 filter. Bottom line, the combinational delay must be less than the clock period, otherwise you will not meet timing closure. For example, if the clock is a 100 MHz and Tcomb = 25 ns, you will not be able to run this filter at 100 MHz. You will need to split it in 3 or 4 parallel filters that run at 33 MHz or 25 Mhz. Then you combine the outputs of the parallel filters back to 100 MHz.
As soon as the number of cofficients is high (assume 3 numerator coefficients and 2 denominator coefficients a1, a2), and I can assure you that meeting timing closure can be really hard. That's why these parallelized IIR filtering techniques were created.
