# Why does this parallel IIR filter have such a weird form?

Referring to "Parallel 1st-order IIR filters" on this wikipedia page, the structure of a 4-parallel IIR filter is discussed. However, the format in which it is implemented seems very odd.

Why is it necessary to iterate the IIR equation N parallel times? Could you not just parallelize it in a direct form. Refer to my chicken-scratch block diagram below.

• Could you draw a slightly better chicken-scratch? Having trouble following it; including the actual $z^{-1}$ delay elements and arrows showing the direction of the signal flow would help. Mar 30 '20 at 13:57
• @DanBoschen Updated.
– Izzo
Mar 31 '20 at 0:28
• Ben identified that your delay element should be $z^{-4}$, which makes sense to me, do you agree? Mar 31 '20 at 23:34
• $z^-1$ in a parallel system corresponds to $z^-4$ in the non-parallel system. I think my delay element is correct as is.
– Izzo
Apr 1 '20 at 0:08
• Yes I see that now! Apr 1 '20 at 0:15

## 2 Answers

The main difference between the form the OP is showing and the referenced solution is that the referenced answer isolates the pole and moves it further away from the unit circle resulting in a more stable design applicable to fixed point solutions. In particular the solution the OP gave has delay accumulation from each element that is within the feedback loop (four multiplier and adder elements) which would limit the maximum clock rate that it could operate in a stable condition for in a realizable implementation.

This is depicted in the diagram below showing the synchronous and combinatorial elements. In order for this diagram to accurately match the first order IIR filter (a single feedback tap), the internal functionality shown must be combinatorial. This will run at 1/4 of the clock rate, but will take significantly longer for the state to settle between clock cycles than the implementation shown in the OP's Wikipedia link copied below this image.

OP's Diagram

Wikipedia Diagram (note this is only showing two of 4 outputs ($$y[4k]$$,$$y[4k+4]$$), in Ben's answer he links a pdf that shows the expanded version of this on p. 35 that shows all four outputs that would be needed after each clock cycle. In either diagraml this partial one or the complete one, the feedback loop is the same, which is the main point: it consists of only 1 adder and 1 multiplier running at 1/4 the clock rate, rather than 4 adders and 4 multipliers in the critical feedback loop).

• But the main point seems to parallelize the IIR computation. Unlike FIR, IIR cannot be simply parallelized, you have to transform the transfer function with pole/zero cancellations
– Ben
Mar 31 '20 at 1:09
• I based my comment on the PDF in my answer. I had read the PDF before seeing the question and I recognized the form that the OP had drawn. It's true the filter will have better stability as the pole is moved further away from the unit circle.
– Ben
Mar 31 '20 at 1:30
• "each adder that is within the feedback loop which would limit the maximum clock rate" - This is what I wasn't realizing. My form imposes a feedback dependency that limits the sample rate.
– Izzo
Mar 31 '20 at 3:55
• No.. there's a mistake in the drawing. The delay should be Z^-4 not Z^-1 We use this form to split an IIR filter in parallel because we cannot run it at the original rate... Check people.ece.umn.edu/users/parhi/SLIDES/chap10.pdf
– Ben
Mar 31 '20 at 22:51
• @Ben So both solve the parallization problem (run the resources at quarter rate - his block diagram with the the linked one). So between the two the linked one could run at a higher clock rate since there is only one add in the feedback loop. As Izzo points out the $z^{-1}$ is running at the lower rate so makes sense. Apr 1 '20 at 0:16

The IIR runs at a reduced rate compared to the sample rate.. For example, if the sample rate is 100 MHz, the hardware clock is 25 MHz. That's why the architecture is so weird like you said.

For the record, it is really hard to meet timing closure in an FPGA when the samplingfrequency is higher than 100 MHz because of the combinational delays between the flip-flops (delay elements). There are strategies to work around this problem :

Split your order-2 or order-1 IIR filters in parallel filters and run them at a reduced rate and combine the outputs to get back to your original sample rate.

Or, use a technique like scattered look-ahead to increase the order of your IIR filters, from 2 to 4. Or from 1 to 2. By using clever pole-zero cancellation, you can meet the timing margin more easily. I used this technique in the past.

In the image below, I explain what causes the combinational delay for a simple IIR order-1 filter. Bottom line, the combinational delay must be less than the clock period, otherwise you will not meet timing closure. For example, if the clock is a 100 MHz and Tcomb = 25 ns, you will not be able to run this filter at 100 MHz. You will need to split it in 3 or 4 parallel filters that run at 33 MHz or 25 Mhz. Then you combine the outputs of the parallel filters back to 100 MHz.

As soon as the number of cofficients is high (assume 3 numerator coefficients and 2 denominator coefficients a1, a2), and I can assure you that meeting timing closure can be really hard. That's why these parallelized IIR filtering techniques were created.

• I understand that the parallelism allows us to update the filter at a slower rate than the sample frequency. However, my "direct form" should be capable of that as well.
– Izzo
Mar 23 '20 at 1:41
• It looks like an interesting link but the fonts in the formulas are all corrupted for me, are they likewise for you @Ben? Mar 23 '20 at 1:44
• @Dan, use acrobat, not google chrome
– Ben
Mar 23 '20 at 1:45
• @Ben much better thanks. To tag just leave out the space so I would be at_signDanBoschen Mar 23 '20 at 1:49
• @Ben I guess there is a LOT more flexibility on the how to message. For details see here meta.stackexchange.com/questions/43019/… Mar 23 '20 at 1:55