Can anyone please help me in simulating a simple BPSK transceiver system that correctly receives a signal through a DUC and DDC? I have attached the screenshot of my Simulink system along with constellation diagrams, spectrums and DUC and DDC filter responses. Below are the specs used in the system:

Binary Generator Specs

Probability of zero - 0.5

Initial seed - 61

Sample Time - 1/10e3 (10 KHz Sampling Frequency)

Samples per frame - 44

Digital Up-Converter Specs

Interpolation Factor - [1 16 2] (Total Interpolation factor - 32)

Here, 3x1 Matrix elements indicate the interpolation factor of the three individual stages of interpolation. Simulink DUC block uses a FIR interpolation filter, followed by a CIC filter and a CIC compensator.

Minimum order filter design - Yes

Two-sided Bandwidth of the input signal - 2e3 (2 KHz)

Source of stopband frequency - Auto

Passband ripple of cascaded response - 0.1 dB

Stopband attenuation of cascaded response - 80 dB

Type of oscillator - Sine wave

Center Frequency of output signal - 100e3 (100 KHz)

Input sample rate - 10e3 (10 KHz).

Digital Down Converter Specs

Decimation factor - [2 16 1] (Total decimation factor - 32)

Minimum order filter design - Yes

Two sided Bandwidth of the input signal - 2e3 (2KHz)

Soure of stopband frequency - Auto

Type of Oscillator - Sine wave

Center Frequency - 100e3 (100 KHz)

Input Sample Rate - 10e3*32=320 KHz

As you can see, I do not get correct BER, which means my signal is getting aliased as I receive through the DDC. As seen from the spectrums, I receive correct frequency translation and correct output sampling rates, which means the signal is getting correctly up-converted.

Please help me in debugging where the problem lies. I presume the problem is with the filtered response. The simulink block allows to modify the filter orders of the FIR interpolator, CIC interpolator and CIC compensator. If anyone could help me in correctly design the system, I would be beholden to you. Thank you

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1 Answer 1


Help design my system would be far more detail than what we typically provide here, but I can give you some suggestions that may help or at least lead to a more concise question.

I do not get correct BER, which means my signal is getting aliased as I receive through the DDC.

Not getting the correct BER does not necessarily conclude this.

In your case the error rate appears to be 50% which suggests your receive data is completely independent of your transmitted data - one possible reason this is if the delay for all the filtering hasn't been properly accounted for when comparing the transmit to the receive signals. Instead of comparing the constellations, consider comparing the baseband modulated signals in the time domain as waveform amplitude versus time to help determine what the actual failure mechanism is. That will show you if everything is fine and you just have the expected time offset, or otherwise give you further visibility into where exactly the problem is occurring (look at the in/out of each block in the time domain).

Once you isolate the block that is not performing as you would expect it to, it will either be quite clear to you what the problem is or you will have a more concise question to ask here.

Good luck!

  • $\begingroup$ Thank you for replying sir. Do you mean that we do not see the BER while doing up and down conversion? Actually I did a very simple experiment by including the Sampling Rate Converter block to do interpolation by 4 and decimation by 4 to get back the original signal. I checked the values in workspace before and after the SRC and made it run for one simulation time unit. The values that I get after down conversion are very small, and are not in terms of 0s and 1s. Because of this the BER gets degraded. $\endgroup$ Mar 15, 2020 at 15:09
  • $\begingroup$ Yes of course it could be in the up and down conversion. My point was to evaluate each block to see if each one is doing what you expect and for many a review in the time domain as a plot of the waveform versus time can be helpful to isolate the issue $\endgroup$ Mar 15, 2020 at 15:17
  • $\begingroup$ As mentione d above about the DUC block, it does 3-stage interpolation, followed by CIC filter and a unit that multiplies the I and Q components with cos and sine respectively, and adds it to get the real translated passband signal. Now, the values of this passband signal ranges from around -2.4 to +2.4. Now, as it goes to the DDC, inverse operations are done to get the complex baseband signal. But the values are not matching with the ones that were before the DUC, because of which the BPSK demodulator demodulates wrong bit values. What is generally done to measure the BER in such cases? $\endgroup$ Mar 15, 2020 at 15:20
  • $\begingroup$ Please do what I suggested and update those plots in your question and then maybe myself or someone else can help further. I can’t suggest anything further from “The BPSK demodulator demodulates the wrong bit values” as it doesn’t really help isolate what is going on, sorry! $\endgroup$ Mar 15, 2020 at 15:44

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