I'm using a Xilinx Virtex 6 FPGA with 200 MHz clock connected to a 1.6 GSa/s DAC to generate sine waves of up to 800 MHz using 8 parallel Xilinx DDS Compiler IP cores.

Initially, I calculate the 32 bit wide phase increment using the formula provided in the manual with a 32-bit wide phase accumulator, 200MHz clock frequency and desired output frequency.

Then 8 DDS modules are instantiated each with a phase offset of $0,\frac 18 \Delta_\phi,\frac28 \Delta_\phi,\ldots, \frac78 \Delta_\phi$. These output 8 samples of a sine wave on every 200 MHz rising clock edge, matching the higher sample rate of the DAC.

The DDS produces correctly sampled output waves up to a frequency of 200MHz. However for f > 200 MHz, the output waves are the wrong frequency. For example, if I input $f =300\,\text{MHz}$, the generated wave is 100 MHz; if I input $f = 400\,\text{MHz}$, the generated wave is 200 MHz.

My suspicions are there is an overflow at some point in the calculation of the phase increment and phase offset values due to their 32-bit width. My question is how would I get around this to correctly produce waves of up to 800 MHz?

I am not concerned with effects of undersampling the higher frequency waves, i just want to see the correct amount of samples per cycle i.e. 2 in the case of $f =800\,\text{MHz}$.

  • $\begingroup$ Maybe using more than 32 bits? Why can you only use 32 bits? $\endgroup$ Feb 14, 2020 at 12:38
  • $\begingroup$ Have you tried using modelsim? $\endgroup$
    – Ben
    Feb 14, 2020 at 13:19
  • $\begingroup$ The simulation behaviour of the core should match the behaviour in real life. $\endgroup$
    – Ben
    Feb 14, 2020 at 13:19
  • $\begingroup$ I've used ISim to simulate the cores and the output matches real life. I think it is a problem using the phase increment formula which is just (f/f_clk) * 2^N where N is the bit width of the phase accumulator.. As the ratio (f/f_clk) > 1 when f > f_clk this causes the overflow so I don't see how changing the value of N from 32 would help anything. I've been following a paper on producing high frequency sine waves that use this exact method so it should be possible. $\endgroup$
    – jake_head1
    Feb 14, 2020 at 13:30
  • $\begingroup$ @user253751 that's nowhere near the problem here. $\endgroup$ Feb 14, 2020 at 14:20

1 Answer 1


So, as far as I understand your system, you've basically taken your target sample stream and decomposed it into 8 polyphase components; thus, each DDS runs at $\frac18$ of the target 1600 MS/s rate, i.e. at 200 MS/s.

Thus, the phase increment that a single DDS does per sample it produces is 8 times the phase increment of the interleaved samples.

Thus, if you wanted to produce a wave at 200 MHz, that means one period of the output would take 8 samples; therefore the output's phase difference between successive samples is $\frac{2\pi}8=\frac\pi4$. And thus, the period, from the point of view of the individiual DDS has a period of 1 sample, meaning $\Delta_\phi =0$! That makes sense: if you want to produce an exact 200 MHz wave, your 8 polyphase components would always be the same samples of a sine wave period.

So, your behaviour is fully expected. When your output frequency is 200 MHz, the individual DDS'es frequency must be 0. You basically work based on aliases.

This has nothing to do with integer overflows, but is just like the math for polyphase signal generation is.

So, nothing wrong here, you'll just have to figure out what the right phase offset per DDS is.

  • $\begingroup$ Yes you are correct with your understanding. I think I understand the issue now. Am I correct by calculating the phase increment of each DDS using f_clk = 200 MHz (from the FPGA) or should I be using f_clk = 1.6 GHz (from the DAC)? Or is the phase increment calculation fine and I just need to find the correct relation between the phase offset of an individual DDS and the other parameters? $\endgroup$
    – jake_head1
    Feb 14, 2020 at 17:12

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