I've developed a radar that I'm using to determine the distance to remote objects. It uses a custom PCB with an onboard FPGA that performs the DSP algorithms. The data from it is then plotted on a host PC. This appears as a 2D histogram where the y-axis denotes the FFT frequency bins (due to the nature of the radar this is proportional to distance) and the x-axis denotes time. The plot (shown below) gives a very strong signal at a distance halfway between the antenna and max range, which I'm unable to explain.
The actual algorithms performed are: an FIR polyphase decimation filter (downsamples from 40MHz to 2MHz) which produces an output 1024 samples in length. Then I run it through a Kaiser window function with a beta of 6, followed by a 1024-point FFT, the result of which is transmitted to the host PC. For each value of t in the plot (the x-axis) the host PC averages over 30 1024-length sequences (averaged element-wise). Since all inputs to the FFT are real, the output is Hermitian symmetric and so I only plot the first 512 values of each output sequence. The strong signal you see above occurs at bins 257 and 258 (indexed from 0). I've tested the radar in an open space where it shouldn't generate any strong signals. I've simulated all of the FPGA logic, so while I can't be sure it's right (I've only formally verified parts of it), I'd be surprised if it wasn't.
What could be the cause of this? Is there some obvious aspect I'm missing? If any of this is unclear or some part of the information I've omitted is important for answering this question (e.g. the equation relating frequency to distance), please let me know and I'll include it.
Edit: more details on acquired signal
This is an FMCW radar. A frequency synthesizer generates sawtooth ramps from 5.3GHz to 5.9GHz over a duration of 1ms. This signal is simultaneously transmitted and mixed back in with the reflected signal. We then measure the difference frequency to back out the distance.
The FPGA modules are timed such that data is only acquired during the synthesizer's ramp period. First, I enable the ramp and power amplifier and (once enabled) begin acquiring data. The data is processed by the FIR filter and then passed through the kaiser window. Once the last sample passes through the FIR filter the ramp and power amplifier are disabled. The processed data (which were stored in a FIFO) are now run through the FFT and then the resulting output is dispatched in packets to the host PC via USB. I use a header sequence, tail sequence, and duplicated packets to try to avoid data corruption/loss. Once the FFT is finished, the process starts again (ramp and power amp enable, etc.).
The FIR filter should take just longer than 0.5ms to acquire all samples, so it should fall within the frequency ramp period.
