I'm using a Xilinx FPGA (Virtex) with 4 DDS cores (each supplied a 250MHz clock) used in parallel to provide a samples to a DAC38J82IAAV from TI, 16 bit DAC running at 1 Gsps. The four cores super sample (interleave their samples) to provide samples at 1 Gsps (250MHz clk * 4 cores = 1 Gsps) for the DAC. I'm trying to output frequencies between 20MHz and 500MHz with the DAC.
The DDS cores are configured in rasterized mode with modulus of 10000. I set the Phase Increment (PINC) to be (desired_freq * 10000)/250 and the Phase offset for each core to be 0, PINC/4, PINC/2, 3*PINC/4.
This works great for generating frequencies above 250MHz, but for frequencies below 250MHz, I see harmonics at Fout, 2*Fout, 3*Fout and so on. I would expect to see harmonics at Fout, Fsample-Fout, Fsample+Fout and so on, which I do see for frequencies above 250MHz.
Why am I seeing multiple harmonics at Fout interval for frequencies below 250MHz?