I have a DPLL that's trying to lock to a DSB-SC input signal with a carrier whose phase is $\theta$. So after some mixing and filtering (Costas Loop), I have these two signals ($\hat{\theta}$ is the estimated phase by the DPLL):

$$ s_I(t) = 0.5x(t)cos(\theta-\hat{\theta}) $$ $$ s_Q(t) = 0.5x(t)sin(\theta-\hat{\theta}) $$

And the output of my phase detector is: $$ q(t)=atan\left(\frac{s_I(t)}{s_Q(t)}\right)=atan\left(\frac{sin(\theta-\hat{\theta})}{cos(\theta-\hat{\theta})}\right)=atan(tan(\theta-\hat{\theta})) $$

But as you know, $atan(tan(\theta-\hat{\theta}))=\theta-\hat{\theta}$ only if $-\frac{\pi}{2}\leq(\theta-\hat{\theta})\leq\frac{\pi}{2}$.

I know how I could adjust $\theta-\hat{\theta}$ so that they fall within the accepted range. The thing is, I don't have access to $\theta-\hat{\theta}$ but to $s_I(t)$ and $s_Q(t)$.

What could be done to guarantee there's no phase ambiguity? I mean, I can adjust only $\hat{\theta}$ since I'm generating it, but adjusting that one doesn't mean that $-\frac{\pi}{2}\leq(\theta-\hat{\theta})\leq\frac{\pi}{2}$ will be true.

  • $\begingroup$ You. don't want to use the $\arctan$ function in determining the phase but rather the atan2 function which gives a value between $-\pi$ and $+\pi$. $\endgroup$ Oct 10 '19 at 19:53
  • $\begingroup$ That’s true, I found out about it after writing the post but I would still have the same problem, I’d still need to make sure $-\pi\leq(\theta-\hat{\theta})\leq\pi$, so how could I achieve it? $\endgroup$ Oct 10 '19 at 21:08
  • 2
    $\begingroup$ Pass $\left(\frac{s_Q(t)}{\sqrt{s_I^2(t) +s_Q^2(t)}}, \frac{s_I(t)}{\sqrt{s_I^2(t) +s_Q^2(t)}}\right)$ as arguments to atan2 and you will get the value of $\theta -\hat\theta$ which is guaranteed to lie in $[-\pi,\pi]$, $\endgroup$ Oct 10 '19 at 21:24
  • $\begingroup$ The phase ambiguity is a real problem that defines the lock range of your DPLL in terms of maximum frequency offset otherwise you can lock to an alias location; often a frequency lock loop is also used to ensure your frequency is within this proper capture range so that you do not get a false lock; or there is an initial frequency search during acquisition prior to the final pull-in of your DPLL. Also, typically the resources to compute an ATAN2 are not necessary in practical implementations as you can sufficiently approximate the phase such as using the cross-product phase detector $\endgroup$ Oct 12 '19 at 1:27
  • $\begingroup$ (See dsp.stackexchange.com/questions/31497/…) $\endgroup$ Oct 12 '19 at 1:28

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