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I have a design in which a signal from ADC is filtered and then played by DAC. In FPGA the real signal is converted to quadrature using DDS with 70 MHz frequency. After filtering, the baseband signal is sent to DAC. DDS of DAC is also set to 70 MHz.

The problem is that there is always a spur in output of DAC at 70 MHz. Noise level is almost -93 dBm and this spur is -82 dBm while the main signal level is -15 dBm.

Level of spur does not depend on the signal level, as long as signal passes through filter. My first guess was that this is because of signal truncation. There are two steps of truncation in design. I have used convergent rounding instead of truncation but the spur is still there; decreased by almost 6 dB but still there. then I wondered that this might come from ADC, but changing the frequency of input signal does not change the spur; It's always at 70 MHz. Then I taught that it might be because of DAC LO but when the signal is in rejection band of filter, the Spur disappears.

Do you have any idea what makes this spur and how can I remove it?

Any help would be appreciated.

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    $\begingroup$ so, that DC component is -67 dB below signal? Sounds not so bad at all, is it worth remediating that at all? What's your quantization noise floor? Is this a problem for what happens downstream with the DAC output? I mean, typically, if this is an RF signal, AC coupling would effectively eliminate the DC offset... $\endgroup$ – Marcus Müller Oct 6 at 12:57
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First question is your DAC AC-coupled? In that case, the AC coupling will remove the DC offset caused by your DDS.

Second question, unless your DAC is perfect, your DAC will also have a DC offset. Do you know what's the typical DC offset level of your DAC? Again, if the DC offset caused by your DDS is less than say 10% of the intrinsic DC offset of your DAC, I don't think it's worth it to fix it.

Third question, is the ratio between the sampling frequency and the signal frequency a whole number? If it's an even number, you should not have any DC offset, but if you have an odd number of samples per period, you could get a DC offset, For example, with a ratio of 5 because you might get two round-ups and three round-downs giving your a negative DC offset.

Here's what you could try:

  1. change the signal frequency so that the ratio between fs and f is not a whole number.
  2. Try to add phase dithering, this could remove your DC "spur"
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