I am using a Hack RF One as SDR and the software GNU Radio to receive and process signals emitted from a drone. Given that the drone is moving and is emitting signals from a wide zone, received signal strengths vary dramatically : if the signal is too large, it over-ranges the ADC input and if the signal is too small, it gets lost in the converter's quantization noise.

At the reception, I have three different gains : RF gain, IF gain and BB gain. RF gain can be set to 0 or 14dB, IF gain from 0 to 40dB by 8dB steps and BB gain from 0 to 62dB by 2dB steps. At the transmission, I keep the transmitting power constant.

For now, my algorithm to manage the different values of gains is the following : Every x seconds, I look at the received digitised signal peak-to-peak value $V_{pp}$ (I take the maximum value V_pp for real or imaginary received signal) and I try to maintain this value into a range such that $V_{pp,lim1} < V_{pp} < V_{pp,lim2}$ , to avoid quantization noise and saturation. To do so, I simply increase or decrease the gain in function of the value $V_{pp}$, starting with IF and BB gains to finish with the amplifying RF gain.

The problem is the following : My algorithm is not optimised. Given that the possible changing steps are not linear and different for every type of gain (14dB for RF, 8dB for IF and 2dB for BB), I sometimes fall into situations where my gains are continuously changing between two situations and do not manage to stabilise even if I keep the distance constant between emitter and receiver.

The question is : how can I manage to have the more constant output amplitude so that my dynamic range is optimised for the ADC?

Constraints :

  • Gain steps restricted : 14dB for RF (0 or 14dB), 8dB for IF (from 0 to 40dB) and 2dB for BB (from 0 to 62dB)

  • Order of changing gains : "Increase or decrease the IF and baseband gain controls roughly equally to find the best settings for your situation. Turn on the RF amp if you need help picking up weak signals" (source : https://github.com/mossmann/hackrf/wiki/FAQ )

  • $\begingroup$ Generally, things like this greatly depend on the modulation you use. What's your modulation scheme, and what's your bandwidth? $\endgroup$ Aug 10 '19 at 18:55
  • $\begingroup$ oh, and very relevant: how large is the change between your signal powers from close to far? $\endgroup$ Aug 10 '19 at 20:23
  • $\begingroup$ I'm using QPSK modulation and my sampling rate is 2MHz $\endgroup$
    – Dylan
    Aug 11 '19 at 10:43
  • $\begingroup$ You mean for same transmitting and receiving powers, how the amplitude of my signal is reduced in function of the min and max distance? $\endgroup$
    – Dylan
    Aug 11 '19 at 10:45
  • $\begingroup$ and fading, yes :) I simply would like to know the dynamic range you need to cover. $\endgroup$ Aug 11 '19 at 10:50

This is a great question and comes down to the AGC design and optimizing the available dynamic range on the ADC, given a receiver minimum SNR, sensitivity and interference rejection requirements.

I first need to know or establish these requirements and then usually start a receiver design from the ADC options available within the cost, power and technology constraints. I work from the ADC in deciding what functionality would be analog and what would be digital (as most functionality can be either in terms of the "radio" operation). That said, the ADC must provide as a minimum the the dynamic range the waveform fundamentally requires (SNR required to meet bit error rate requirements for example) and then any excess can be utilized for digital AGC capability, thus simplifying the front-end by allowing for digital filtering of out of band interference or multi-carrier applications with wider dynamic range between channels. This approach would use an analog AGC to set the input signal to the optimum level below full-scale (see chart at bottom of post for that) at the input to the ADC and then provide digital AGC implementation after channel selection or out of band interference (that ended up controlling the pre-ADC signal level) has been removed.

The analog AGC can be stepped with fixed gain amplifiers or attenuators as you are doing, or can be implemented with variable gain attenuators or amplifiers that provide a smooth adjustment of signal level with a control voltage, maintaining a constant level at the ADC input.

Below shows a diagram for the key concepts and considerations in the mixed signal AGC approach with fixed gain steps prior to the ADC, showing the hysteresis to avoid chatter when crossing thresholds that would change the input power. The upper and lower range for the signal varies between the minimum signal level to meet the receiver design objectives under worst case interference conditions ("blockers") and the maximum signal where performance is also still achieved (before degradation due to clipping).

AGC diagram

Importantly consider what occurs in a flawed digital AGC implementation with stepped gain front-end control as shown in the diagram below. The AGC as a loop will have a loop BW set to be as fast as possible to correct for amplitude changes without being so fast so as to track out amplitude components of the modulation (for waveforms that have amplitude modulation components such as OFDM prior to demod, QAM, etc). My rule of thumb is using a loop bandwidth anywhere from 1/20th to 1/50th of the symbol rate.

That said, when an AGC controller steps the gain of the analog front-end, following the hysteresis diagram above, the signal at the demodulator will immediately drop, the digital AGC will detect the change in power level and correct the level within the time allowed by the loop BW (again by design it cannot correct too fast or will remove AM modulation signal of importance).

Digital AGC

A solution is to add a calibrated compensation in the digital AGC, that when upon controlling the front end gain, a compensatory gain is added post ADC prior to the digital AGC. This will minimize the step to a much shorter glitch (since the time between the two cannot be 0 but can be minimized), resulting in much less disruption to the receiver when changing front-end gain.

Step Gain Compensation

Important to the design considerations mentioned for AGC, both digital and analog, I have developed the following useful curves showing what level to set the AGC below full scale (in this chart, "full scale" is where a single complex IQ tone would clip, so the equivalent clipping for a real sine wave would be -3dB on the horizontal axis).

This is a very useful chart for maximizing the dynamic range with an AGC, and equivalently shows where the rms level of a modulated waveform needs to be digitally in order to minimize the number of bits in the datapath without distorting the signal due to clipping. Specifically this curve shows the optimum operating point for a Gaussian distributed waveform (as are well approximated by most modern modulations) between two distortion sources: quantization noise and clipping.

Two examples of using this chart: At ADC input and at baseband digital modem of the IQ waveform, both assuming Gaussian distributed signals.

ADC Input example: Suppose we wanted to maximize the available dynamic range for an 8 bit real converter of a modulated signal at IF. The purple line on the chart is for 8 bits and shows that the combined noise between clipping and quantization is minimized when the input signal is AGC'd to be 12 dB - 3 dB = 9 dB below the same level where a sine wave would clip. At this level we would have 40 dB SNR due to clipping and quantization: the total power due to clipping and quantization would be 40 dB below our signal.

Modem input example: We want to know the minimum number of bits required on I and Q for a waveform where we need 20 dB SNR for demodulation to meet design objectives. We could achieve that with a 4 bit data path IF we set the IQ signal level at the modem input to be 8 dB below the full scale IQ radius.

If the rms level of the signal is set too high, excessive clipping noise results; if it set too low, excessive quantization noise results--- or if we have excess dynamic range in the ADC (which we want to simplify the front-end), if we set it too low we lose dynamic range.

ADC input signal below full scale

This point is further demonstrated with the following graphic. Many will see the few samples exceeding the range of the ADC and decide that the input signal is too high as clipping is occurring. However, as is clear from the chart above, they may lower the input signal level (set AGC level lower) to eliminate any clipping noise- but they will likely then be past the minimum- in which case more quantization noise is added for a net loss. The ideal operating point will have some amount of clipping, and we win overall by allowing that.

ADC Full Scale


To avoid quantization or limit cycle oscillations, you can add hysteresis to your AGC decision loop (a form of "debouncing").

  • $\begingroup$ How would you implement the add of a hysteresis to my algorithm? Hysteresis is useful to be conscious of the "direction" of the algorithm but I do not see the utility here. $\endgroup$
    – Dylan
    Aug 12 '19 at 10:24

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