I am designing an IIR filter with fixed-point arithmetic and I have to select the proper length for the accumulator and product. I would like to know a standard to follow in order to choose its length. I have selected the Direct Form 1 topology to implement a 6th order digital filter (instead of a cascaded second-order block), as it has only only one point where the sum is done and thus only one point which has to be taken care of when considering quantification error and overflow (correct me if I am wrong!).
For the ACCUMULATOR, I assume that I have to consider the worst case of summing numbers with N bits, so the answer should be N+M bits to avoid overflow, where M represents the quantity of numbers which it is summed.
For the PRODUCT, multiplying two numbers of N bits, in the worst scenario gives us a N+N=2N bits result.
I don't know if it is this easy or if I am skipping an important concept.
If you have experience in this field, any documentation about designing IIR filters on microcontrollers will be welcomed.