# Reducing hardware demands for an adaptive and complex-coefficient FIR filter

I want to implement a complex-coefficient FIR filter with adaptive coefficients in hardware (FPGA). The inputs to this filter are the I and Q channel as separate wires. The outputs are the filtered I and Q channel as separate wires.

I realized that a complex-coefficient FIR filter needs 4 times the multipliers and 2 times the adders of a real-valued FIR filter, which becomes clear when looking at the product of two complex numbers:

$$(a+jb)(c+jd) = ac - bd + j(bc + ad)$$

Are there ways for reducing the hardware demands apart from making sure that the multipliers are as narrow in terms of bitwidth as possible (as long as quality is still acceptable)?

EDIT: I forgot to mention that I am implementing in fixed-point, not floating-point.

• Yes, there is a lot of research on that. Just search "fpga complex multiplication" in IEEE Xplore or google scholar. An alternative is to see if your FPGA vendor libraries include a block for complex multiplication, and just use that. – MBaz Jun 3 at 15:16