I am implementing a filter that is FIR on verilog HDL ,, I understand what happen in the filter well, I mean the delay, multiply and sum, the problem that I can't imagine how can I get the desired output as it is implemented in an OFDM communication system enter image description here

that is the description of what should happen to avoid ISI ...regarding the coefficients part of the FIR, there is some part of the actual symbol without the CP that will not be attenuated using the filter, should I multiply by one? I mean pad the ROM coefficients with ones, or should I make another path for the unmultiplied part to consume less power and hardware ...any ideas, please?


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