I'm working on a real-time audio processing project in which I have to downsample a 44.1 kHz to a yet-to-be-determined lower sampling rate essentially for reducing computational complexity. I'm looking for a decent downsampling filter, and I found articles suggesting both IIR (mainly elliptic) and FIR (mainly minimum phase). FIR minumum phase filter wouldn't necessarily work for me, because I need a linear phase filter. So the options are either linear phase FIR that could have a considerable latency in it or a double-filtering IIR (MATLAB filtfilt command) that first filters forward then backward.

What are some pros and cons of FIR and IIR as downsampling filters? Which is more practical in a real-time application?


If linear phase is a requirement, that will probably steer you toward an FIR implementation. It is possible to build IIR filters that have approximate linear phase, but it is easy to design a linear-phase FIR.

If you're concerned about latency, forward-backward filtering as in filtfilt isn't really a good option. In general, it's really meant to be used an offline process, since to implement the technique exactly, you have to run the entire signal through forward, then do the same in reverse. That implies that you have access to the entire signal at once, which is not commensurate with low delay.

In general, an FIR filter will require a higher order for a given set of performance requierments. However, FIR filters bring some real advantages, such as guaranteed stability, lower susceptibility to roundoff errors (since the quantization error doesn't get fed back through the filter, although you can compensate for this with some increased complexity), and simply-achieved linear phase response. In addition, efficient FIR filter implementations are available for many processor architectures, mitigating the cost of the extra taps somewhat.

Another way to mitigate the extra-tap cost for FIR filters in your situation is to take advantage of efficient multirate signal processing techniques. Specifically, you can use a polyphase decimation approach to significantly reduce the number of computations that you perform in the process of decimating your signal. This has the effect of decreasing the number of effective taps (in terms of computational complexity) in the decimation filter. In addition, if you need to decimate by a large factor, then multistage approaches can help further reduce your load. Lyons' introductory DSP book has some good easy-to-read material on these topics.

Given more specific parameters of your system, one could make more pointed recommendations. What are your filter design requirements? What sort of computational capabilities does your platform have? What sample rate will you decimate to?

  • $\begingroup$ Polyphase decimation is exactly what I was looking for! Thanks = ) $\endgroup$ – Phonon Nov 3 '11 at 14:58
  • $\begingroup$ @Phonon And if you want to kick it up even further, look into 'CIC' (Cascade Integrator Comb) implementations. Thats a technique usually used for when the difference in sampling rates is very big. $\endgroup$ – Spacey Nov 4 '11 at 0:37
  • $\begingroup$ CIC filters are popular for hardware implementations (such as in FPGAs) because they don't require any multiplication, only delays and adds. This comes at the expense of some degrees of freedom for what the filter's response actually looks like. If you have tight requirements for the decimator's frequency response, you can do better than CIC approaches, provided you can accommodate the workload. $\endgroup$ – Jason R Nov 4 '11 at 1:51
  • $\begingroup$ @JasonR Youve peaked my curiosity - what is better than CIC? (I am assuming you are still talking about doing better that CIC for FPGA or are we talking about offline?) $\endgroup$ – Spacey Nov 4 '11 at 22:41
  • $\begingroup$ My comment was in reference to the fact that you have comparatively little control over the frequency response of a CIC filter when compared to a general FIR filter, which you can design to have an arbitrarily sharp cutoff if you give it enough taps. As with most filter design problems, you need all of the performance specs on the table in order to pick the best approach. $\endgroup$ – Jason R Nov 5 '11 at 2:24

How low do you mean by "low latency"?

If you mean below 1 mS with a large sample rate reduction, then a minimum phase FIR may be required. If you mean around 1/30th of a second, then you might even be able to implement an efficient linear-phase FIR filter using an FFT overlap add/save (fast convolution) approach.


A little gotcha regarding time complexity: FIR filters are vectorizable, which really helps in modern CPU architectures. Furthermore, IIR filters take a performance hit because the current output value depends on earlier output values, which removes the advantage of pipelining.


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