For implementing DSSS, it is understood that each raw data bit needs to be encoded as a new recognizeable/identifiable bit pattern.
In many literature involving DSSS, there is mention of using PN sequences involving LFSR (linear feedback shift registers).
It appears that maximal length linear shift registers have a maximal length that is always an odd-valued number, such as 15. So, while LFSR generators can be relatively fast and hard-ware implementable, there could be a hardware implementation problem elsewhere.
A pseudorandom sequence from a maximal length LFSR has bit pattern that has an odd number (such as 15 bits). So if (for example) the raw data bit has a bit-rate of 1 bit per second, then to encode each raw data bit with this 15 bit pattern would require the PN generator to operate at 15 bits per second (ie. 15 times higher clock rate than the raw bit rate).
Will this mean that we have to find hardware that generates a clock rate (for the PN generator) having 15 times the frequency of the raw bit rate?
Initially, I was thinking that a high frequency clock could be used as a reference. However, conventional flip flop frequency dividing methods divide frequencies by even amounts, like divide by 2, divide by 4 etc. There is no option for 'divide by 15' (or divide by an odd number).
So if I want to use LFSR PN sequence patterns for encoding raw data bits, then what kind of method should be used? Is this the usual problem faced when using maximal LFSR generators for encoding raw data bits?
My assumption is that a maximal LFSR produces a repetitive cyclic pattern.... such as 0100101 (eg. 7 bit sequence for a 3 bit LFSR), which keeps repeating as 0100101. So at the beginning of every repetition cycle, we can use this pattern to encode our raw data bit.
So a raw data bit such as '1' needs to be translated to this long pattern 0100101. And raw data bit '0' needs to be translated to the negative version of the pattern, such as 1011010. The problem is .... 7 bits is an odd number. So if the raw data bits need to be processed at 1000 bit per second, then we would need a PN clock rate that is at 7000 bits per second.
Due to the odd-valued number of bits, is there generally going to be an issue with coming up with a system for generating the clock rate that is 7 times higher than the raw data rate? I can understand that generating 8 times data rate would be relatively easy to do, because 8 is a 2^N value.
I'm thinking it would have been extremely nice if nature had allowed for maximal length LFSRs to be produced with even-values for maximal lengths.
Would fractional DDS type frequency generation methods be used instead?
Thanks for any comments in advance!!