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For implementing DSSS, it is understood that each raw data bit needs to be encoded as a new recognizeable/identifiable bit pattern.

In many literature involving DSSS, there is mention of using PN sequences involving LFSR (linear feedback shift registers).

It appears that maximal length linear shift registers have a maximal length that is always an odd-valued number, such as 15. So, while LFSR generators can be relatively fast and hard-ware implementable, there could be a hardware implementation problem elsewhere.

A pseudorandom sequence from a maximal length LFSR has bit pattern that has an odd number (such as 15 bits). So if (for example) the raw data bit has a bit-rate of 1 bit per second, then to encode each raw data bit with this 15 bit pattern would require the PN generator to operate at 15 bits per second (ie. 15 times higher clock rate than the raw bit rate).

Will this mean that we have to find hardware that generates a clock rate (for the PN generator) having 15 times the frequency of the raw bit rate?

Initially, I was thinking that a high frequency clock could be used as a reference. However, conventional flip flop frequency dividing methods divide frequencies by even amounts, like divide by 2, divide by 4 etc. There is no option for 'divide by 15' (or divide by an odd number).

So if I want to use LFSR PN sequence patterns for encoding raw data bits, then what kind of method should be used? Is this the usual problem faced when using maximal LFSR generators for encoding raw data bits?

My assumption is that a maximal LFSR produces a repetitive cyclic pattern.... such as 0100101 (eg. 7 bit sequence for a 3 bit LFSR), which keeps repeating as 0100101. So at the beginning of every repetition cycle, we can use this pattern to encode our raw data bit.

So a raw data bit such as '1' needs to be translated to this long pattern 0100101. And raw data bit '0' needs to be translated to the negative version of the pattern, such as 1011010. The problem is .... 7 bits is an odd number. So if the raw data bits need to be processed at 1000 bit per second, then we would need a PN clock rate that is at 7000 bits per second.

Due to the odd-valued number of bits, is there generally going to be an issue with coming up with a system for generating the clock rate that is 7 times higher than the raw data rate? I can understand that generating 8 times data rate would be relatively easy to do, because 8 is a 2^N value.

I'm thinking it would have been extremely nice if nature had allowed for maximal length LFSRs to be produced with even-values for maximal lengths.

Would fractional DDS type frequency generation methods be used instead?

Thanks for any comments in advance!!

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In your title and your question overall, you confuse bits and symbols. Not a big deal – we can just work with the idea that we use a constellation where one symbol is equivalent to one bit (e.g. BPSK). But remember that there's no restriction that says you can't DSSS e.g. a 64-QAM modulated symbol stream. (In fact, that's what IEEE802.11b does, iirc).

I'll hence use "symbol" in place of "bit" where I cite you below, whenever it doesn't make a difference. When it does, I'll try to explain.

Will this mean that we have to find hardware that generates a clock rate (for the PN generator) having 15 times the frequency of the raw symbol rate?

Yes! We call that higher rate chip rate, by the way.

Initially, I was thinking that a high frequency clock could be used as a reference. However, conventional flip flop frequency dividing methods divide frequencies by even amounts, like divide by 2, divide by 4 etc. There is no option for 'divide by 15' (or divide by an odd number).

Well, you can certainly build a digital counter that counts to 15 and resets – your 1/15 clock divider. So, I think you might be imagining problems where there aren't problems. It's not as trivial as a $2^N$ counter, but honestly, a $2^N-1$ counter is just either a $2^N$ counter where you reset all bits to 0, but the lowest bit to 1 (giving you a single count of headstart), or really just a counter with a $N$-input NOR gate. Or really, just a counter that can compare to an arbitrary value. All these aren't hard to build. This isn't the 1960s!

So if I want to use LFSR PN sequence patterns for encoding raw symbols, then what kind of method should be used? Is this the usual problem faced when using maximal LFSR generators?

The thing is even easier: You've got a device that repeats itself every 15 states, and changes at the high clock rate. Why not simply use that exact device to build your frequency divider? You could just compare all the state of SR to the one state on which you output a pulse. Done!

But again, integer frequency division really isn't that hard to implement at the rates you're probably worried about.

As another matter of fact: you'd probably not even use the higher frequency as reference, but a lower frequency, from which you synthesize the symbol and the chip rate, and quite possibly also the RF local oscillator. Since the relationship between chip and symbol rate is a rational one, a relatively simple integer-N synthesizer might be used, but frankly, aside from spur performance, there's little reason not to go to fractional-N synthesizers – which, by the way, are especially made for such systems.

Due to the odd-valued number of bits, is there generally going to be an issue with coming up with a system for generating the clock rate that is 7 times higher than the raw data rate? I can understand that generating 8 times data rate would be relatively easy to do, because 8 is a 2^N value.

There's no hard tasks here. Count to 7, emit a pulse, reset your counter. Counters are relatively easy to build capable of high clock rates.

Would fractional DDS type frequency generation methods be used instead?

Not quite sure what fractional DDS is, but a DDS method involves jumping through a table at high rates, to produce lower-frequency tones. I don't even think that's easier than a odd-number-counter to build a frequency divider. DDS is generally used to produce tones, not digital clocks.

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  • $\begingroup$ Hello Marcus! Thanks very much for your time and help for addressing my question. I haven't confused bits and symbols. I just kept the language simple. A single raw data-bit is merely re-represented as a string of bits. So 1 raw data bit symbol gets re-represented as a longer digital codeword (also a symbol). It's all a matter of perspective. The reason I asked about odd-numbered maximal length LFSR sequence patterns is because DSSS discussions involve LFSRs. But they never seem to show how they fit that pattern of odd-valued number of maximal bits into 1 raw data bit time. $\endgroup$ – Kenny Mar 21 at 10:36
  • $\begingroup$ Marcus .... also, I assumed that flip-flop LFSR hardware is used to generate the PN codes efficiently - as compared with using a micro-controller. My example of a length 15 LFSR was just to keep things simple. For relatively long sequences - flip-flop LFSR are advantageous, right? I also didn't know that it might be necessary to take a low frequency reference signal to generate a high frequency signal for the chip rate clock. That definitely helped a lot. Earlier, I should have typed fractional digital frequency synthesiser .... not DDS. Thanks once again. Appreciated. $\endgroup$ – Kenny Mar 21 at 10:46
  • $\begingroup$ I never mentioned microcontrollers. I'm a bit confused about what you're trying to discuss in your comment, @Kenny? $\endgroup$ – Marcus Müller Mar 21 at 17:03
  • $\begingroup$ Apologies Marcus. The part about micro-controller was just relating to using a software programmed device to generate the PN sequence rather than using the basic hardware flip flop device. You definitely helped me a lot about possible methods for translating each raw data bit (at basic raw bit rate) to the new sequence (at N times the bit rate, where 'N' is an odd-valued number - due to the odd-number of LFSR unique states during normal operation). It didn't occur to me until recently that converting a raw data bit to a max LFSR PN sequence would require fractional N methods.Thanks again!! $\endgroup$ – Kenny Mar 21 at 21:56
  • $\begingroup$ Marcus - also, I forgot to thank you for the details about using a circuit or device to use the PN clock to divide down the PN clock frequency. So if the PN clock frequency is suitably chosen, then it could be divided down to raw bit rate. Generally appreciated your help and time! Thanks very much Marcus. $\endgroup$ – Kenny Mar 21 at 22:15

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