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I am using FPGA to generate 10Mbaud QPSK signal in two channels corresponding to two quadratures. Upsampling to 1GSample/s (using raised cos filter for interpolation) and complex upconversion (f_up=250MHz) is done in FPGA. This signal is sent to a DAC and detected back-to-back using Tektronix rsa607a spectrum analyzer. I sent 200k sampes and detected them using the analyzer. enter image description here

This is a screenshot form the measurement. On the right side is unzoomed waveform in time where red dots represent sampling points in demodulation. On the left is constellation for the whole stream. As you can see the analyzer synchronizes well with the middle of the captured signal, however it goes off sync with time. If I measure shorter intervals EVM gets smaller. On the left side you can see measured frequency error which is the difference between transmitter frequency and analyzer's internal clock. This error is obviously different with time which tells me the FPGA clock might be unstable. However, I did other measurements when offloading a sine tone where I don't see these frequency drifts. Does anybody have intuition what can be the cause of this problem?

Cheers, D

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  • $\begingroup$ In order to receive the QPSK signal properly you need to to carrier sync and symbol sync. The only way around that is to provide the timing information to the receiver, which you don't want to do in any non-trivial application. $\endgroup$ – MBaz Feb 15 '19 at 15:09
  • $\begingroup$ Thank you for the answer. Sure, I agree, as you can see the spectrum analyzer synchronizes itself, but only to some average carrier frequency it recovers from the captured stream. However if I use an AWG to generate QPSK the signal looks much much better. Therefore, something is very wrong on the FPGA side, and I don't see what it can be since apparently its clock is stable. I am just wondering if this effect of frequency drift can be caused by something else. $\endgroup$ – Dino Feb 15 '19 at 16:04
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    $\begingroup$ I'd test with a sequence of fixed symbols just to check whether your upsampling works. But, I'm fully with MBaz here: you might be simply not be able to tell whether the problem is on the TX or RX side $\endgroup$ – Marcus Müller Feb 15 '19 at 16:16
  • $\begingroup$ (1) There is no such thing as a perfectly stable clock (2) If you don't see the constellation rotating, then the device may actually be carrier synchronizing. (3) If the Rx EVM gets worse with time, that is the classic behavior of a (time-varying) frequency delta between Tx and Rx symbol clocks, which is also unavoidable. You may want to tell the analyzer to re-synchronize every once in a while; how often, depends on the delta. $\endgroup$ – MBaz Feb 15 '19 at 16:49
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The problem was that the FPGA clock was significantly different than the clock from all other devices. It was not calibrated properly in regard to some universal frequency reference.

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