# Moving average and linearization of two piecewise linear systems

I have 2 oversampling ADC's running parallelly, each to process data in a specific range of the input as shown below: Each ADC can process only half cycle range of a sine wave. Each ADC adds its own gain/offset errors. Input is simultaneously applied to different ADCs. Assume one conversion cycle is 1ms and there are 1000 clock cycles (sampling clock).

If the input is of low frequency occuring completely in ADC-1's range or ADC-2's range for one conversion cycle, compensation the gain/offset errors (o1,g1 or o2,g2) of those ADC's respectively is straightforward.

The problem arises during filtering where I need to (moving)average the output from two ADCs which have a different offset and gain errors associated with them. This is where I am stuck.

For simplicity, the filter can be considered a First order Accumulator, (1/z-1). It just averages the 1000 samples.

Below is what I tried:

Since the values o1,g1 and o2,g2 are linear with the number of clock cycles, I tried to find to find a linear equation for them by the following methods: Now I got four equations for ADC-1 and four for ADC-2 (by matching the input and output of separate ADC's - after the filter - in the following conditions): (after fixing tstart): Eqs-1:

• o1=a*n+b
• g1=c*n+d

(after fixing tend): Eqs-2

• o1'=p*n+q
• g1=r*n+s

(Similarly for ADC2)

Through which I can correct the following samples occur sequentially in a single conversion cycle:

• n1 samples from ADC-1 (correct using Eqs-1), n2 samples from ADC-2 ;where (n1+n2=1000)
• n3 samples from ADC-2 , n4 samples from ADC-1 (correct using Eqs-2) ;where(n3+n4=1000)

Now, I am stuck what if the following happens:

• n5 samples from ADC-1, n6 samples from ADC-2, n7 samples from ADC-1 (where n5+n6+n7=1000)

This is where I thought, thinking of the filter (1/z-1) as a convolution would help, as I could design the convolution mask differently. Normally, the convolution mask for moving average would look like below:

mask=[1 1 1 1 1 1]; <-- add the factor due to o1/g1 here, modifying each element with 1*(factor), where factor depends on o1/g1 in case of ADC-1

But I am not sure if that would help fixing the problem. Am I making this problem more complicated?

• Just to verify: are the ADC synchronous or interleaved? Especially, the kind of filter you need would also be dictated by how synchronous the different ADCs are; so, is there a specification of the relative jitter of these? – Marcus Müller Feb 15 '19 at 10:20
• also: gut feeling: at 1ms conversion time, you can choose from such a humongous range of ADCs that there's pretty certainly one with one bit ADC resolution more than your current ADCs, and you can bias that to cover the full sine wave. – Marcus Müller Feb 15 '19 at 10:23
• @MarcusMüller Well, the ADCs are synchronous. There is no specification of jitter - Just an Ideal model with gain/offset errors only. – sundar Feb 15 '19 at 10:28
• ok, that would mean that it's very desirable that the impulse response is relatively flat to ignore any jitter – Marcus Müller Feb 15 '19 at 10:34
• @MarcusMüller Well, I need the impulse response of the filter to be a line matching to a specific slope/offset (with different weights). I tried to think more about this problem and posted a new question - dsp.stackexchange.com/questions/55496/… – sundar Feb 15 '19 at 10:56