What type of low-pass filter to use for gyroscope filtering in control application?

Question

I am using a gyroscope to generate a feedback signal that drives a motor to resist rotation, just as in a camera gimbal.

The gyroscope is sampling at 32 KHz with a bandwidth of 8 KHz, and my control loop is running at 1 KHz. Hence, I need to remove frequencies above 500 Hz. At the same time, I need to introduce as little delay as possible in order to be able to use a high control gain. I've attached the FFT of the sensor noise (source).

I am a little overwhelmed with the amount of choice available when it comes to filtering this signal. What filter properties should I be looking for? Are there any particularly suitable filters? This is implemented on an FPGA, so computational cost is not a constraint.

Answer 1

The lower the cut-off frequency of the anti-aliasing filter, the higher the delay thus degrading your phase margin. You need to be really careful when implementing an anti-aliasing filter in control loops applications.

First question, what is the amount of noise above 500 Hz? Based on the picture, you have noise at about 3 kHz, the main purpose of your anti-aliasing filter is to remove this spike, I would not worry too much about content between 500 Hz and 3 kHz.

Second question, what is the bandwidth of your control loop? 100 Hz? This is not the same as your sampling frequency. Typically it should be BW <= Fs/10. In your case BW <= 100 Hz.

Third question, what amplitude of aliasing can your application live with? If the bandwidth of your control loop is 100 Hz, aliasing occuring at f > 100 Hz will not really impact your performance, you only need to focus on aliasing that occuring at f <= 100 Hz. Even if there's aliasing occuring, if it less than say 1% of the signal of interest, you can probably neglect it.

Fourth question, can you run your control loop at 32 kHz? You would not need an anti-aliasing filter then. (I'm assuming that there's already an analog anti-aliasing filter in the gyroscope).

Based on the information we have, here's what I would do :

If you cannot sample faster than 1 khz, the biggest problem is that the 3-kHz spike will alias to DC (or near DC) . So you need to filter it. I would design a notch filter that removes your 3 kHz spike. This notch filter will add a smaller delay compared to a low-pass filter with a 500 Hz cut-off.

However, if you can sample faster, say 4 kHz, then the 3 khz spike will alias at 1 kHz which should be outside the bandwidth of your controller. In that case, I would only design a simple low-pass filter with a high cut-off frequency.

Edit : You mention you have an FPGA. In that case keep your sampling at 32 kHz and design a controller with a Bandwidth of like 100 Hz. In that case you don't need to worry about aliasing and noise since the noise will be outside the bandwidth of the control loop.