I'm trying to determine whether an application I have in mind is feasible with currently available DSP technology (DSP chips and ADCs).

I want to eliminate an interfering signal using an LMS adaptive filter. I have access to the source of the interference.

The bandwidth of the interfering signal is in the order of 1MHz (maybe a little less, but just as a conservative assumption, let's say 1MHz). The bandwidth of the signal I want to measure can be higher; possibly in the order of 10MHz or 20MHz.

EDIT: I estimate that the application will require sampling at no less than 12-bit resolution.

Does the above sound feasible? Could you suggest some DSP chips that you'd estimate could potentially handle the above workload?

If it sounds like it's not feasible, can you give an estimate of what you think would be the highest bandwidth that current DSP chips could handle?

You may assume that the DSP chip will be doing exclusively this; or maybe just some "lightweight" additional work.


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    $\begingroup$ 20 MHz signal bandwidth is pretty LMS processible in real-time (assuming 8 bit samples). You might consider using external ADC chips though. But I believe, even on chip ADC's can be fast enough to handle this. You know where to look for those chips right? $\endgroup$ – Fat32 Jan 21 '19 at 17:03
  • $\begingroup$ @Fat32: Huh --- I thought I had mentioned in the original message that I estimate I may need to sample at no less than 12-bit resolution (I will edit it to clarify). When you say "where to look for those chips", are you talking about the ADCs? Analog Devices seems to offer a good selection of them (that's even excluding the LT models they list now). If you were referring to DSP chips fast enough for this, with suitable on-chip ADCs, well, not necessarily --- any pointers would be appreciated. $\endgroup$ – Cal-linux Jan 21 '19 at 18:17
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    $\begingroup$ Hmm ok. 12 bits may be even 16 bits. You shall look for Gigasamplers for digital oscilloscopes... They are not 16 bits though. One thing further, you can combine a number of (say N) slower ADC's into a circular multirate structure to achieve N times faster sampling, with some good clock syncronisation too, if a single chip does not satisfy your goals. Yes I mean TI, ST, ADI, NI, NXP kind of vendors' pages... Sorry I dont have a catalog now to select or offer. $\endgroup$ – Fat32 Jan 21 '19 at 18:26
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    $\begingroup$ you could probably use an FPGA for that. Though FPGA design has a steep learning curve, it is sometimes the only solution. $\endgroup$ – Ben Jan 21 '19 at 22:57
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    $\begingroup$ DSPs aren't generally "faster" than CPUs; on the contrary, their clock rate is typically significantly lower. However, they are geared towards very specific operations, which they implement very fast. Whether your specific problem even maps to the abilities of just any DSP isn't a given; plus you'd still need some application processor, typically, with which you control your overall system. Whatever you'd do, you'd always first write a proof-of-concept on a PC, if that's possible, especially to have something to analyze; without knowing what the computationally hard things are, how would … $\endgroup$ – Marcus Müller Jan 22 '19 at 20:31

This is a pretty benign requirement. The Open Source software defined radio community does significantly more than 100 MS/s complex samples in software running on stock PC hardware. The samples come from stock SDR hardware.

However, you wouldn't be doing a 100s of taps long channel estimator / LMS filter at that rate.

It's impossible to estimate the computational complexity of your problem without at least knowing what kind of interferer you want to cancel. However, 10 MS/s really doesn't sound dramatic at all.

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  • $\begingroup$ Given the discussion above, I have (at least for the time being) unmarked this as the answer --- though I agree with implementing a proof-of-concept/prototype version on a desktop PC, I still think that dedicated DSP hardware may end up being the better-suited alternative. So, that brings me back to the original question, which given the comments above, I'm now unsure whether the above answers. $\endgroup$ – Cal-linux Jan 22 '19 at 20:59
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    $\begingroup$ The title question is impossible to answer: "Highest achievable rate" means you'd have to first specify what you need in processing, exactly. You also don't care about the highest rate at all – you need to know what hardware can solve your problem. Be sure to ask the questions you want an answer to! $\endgroup$ – Marcus Müller Jan 22 '19 at 21:01
  • $\begingroup$ also, honestly, there's zero proof that one or the other (standard CPU vs dedicated DSP hardware) is better suited for your problem. So, not quite sure where you get your conviction that dedicated DSP will be better suited – remember, "better suited" also means you'll have to be able to use it. $\endgroup$ – Marcus Müller Jan 22 '19 at 21:02
  • $\begingroup$ (again, 10 or 20 MS/s and a simple adaptive filter really is far below the threshold where I'd even consider using something as complex as a DSP board, leave alone developing one on my own or doing a complex FPGA design. Just run it on a CPU, you'll probably be fine. These rates aren't "high".) $\endgroup$ – Marcus Müller Jan 22 '19 at 21:06
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    $\begingroup$ I guess the best solution will be for me to post a separate question, narrowing down what I'm asking. In a nutshell, as much as in your answer you suggest that my problem seems manageable with PC hardware, and you stated that as an estimate, without knowing specific requirements; well, I'd like to get an estimate like that for DSP chips. You did emphasize that the requirement does not look intimidating, but I wonder if that statement is 100% specific to solving the problem on PC hardware. $\endgroup$ – Cal-linux Jan 23 '19 at 17:26

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