I am trying to code a QPSK transmitter in VHDL but first I want to create one out of Simulink blocks and translate it into VHDL code. I am using an example project for the PlutoSDR as a guide.

This is the block diagram: enter image description here I ran into the following error for which i used Simulink's "fix" option and got this project to compile: enter image description here

When i run this project this is the output i am seeing on Constellation Diagram 1 & 2:

What's happening is the points on the diagrams are continuously moving in a "circular" way. I've uploaded two GIFs of the constellation diagrams 1&2 from my Simulink project.

Constellation Diagram 1: Constellation Diagram 1

Constellation Diagram 2: Constellation Diagram 2

The output of Constellation Diagram, however, does not move and looks like this:

Constellation Diagram

This is the output of the example on the Mathworks website (guide) seen as "Constellation Diagram" in the block diagram above.

My questions: Why did i have to put "Single Task Rate Transmission" boxes into my project as suggested by Simulink? Why do Constellation Diagram1 and Constellation Diagram2 "dance" around like this? What am i missing?

Thank You!


1 Answer 1


You are seeing the "Digital IF” carrier assuming you are modelling what you want to implement digitally in VHDL. The sine and cosine blocks together with the multipliers and combiner perform a frequency translation from DC to the carrier mentioned. Thus the constellation at this point is really not observable as it will be "spinning" at this carrier rate. (The constellation as observed in the upper figure is at DC and to note it appears to be sampled at 2 samples per symbol, which is typical, so it is really every other sample (the ones on the diagonals) that represents the QPSK constellation at the correct symbol sampling locations).

To observe the constellation you would need to frequency shift the signal back to DC while being careful not to introduce phase and frequency offsets, or shifts in sample timing (a receiver does this with carrier and timing recovery loops so that it can run completely on an asynchronous clock from the transmitter).

(To note, an optional approach is "Zero-IF" where you implement the frequency translation in the analog domain using an IQ mixer (which is the same functional block with analog components)

  • $\begingroup$ So i added cos(pi/4) and sin(pi/4) like this: block diagram but i am receiving noise. Any ideas about what im doing wrong? Also do you have any suggestions for how to go about writing VHDL code to do this? I have no experience with wireless digital systems and trying to learn how to make this work. Thank you! $\endgroup$
    – vaspurakan
    Commented Nov 17, 2018 at 21:02
  • $\begingroup$ I am sorry I gave you bad direction as I thought your were observing the output after your QPSK block in the upper figure. I also see that you are not actually trying to simulate but you want to implement a QPSK transmitter, in which case the Sine and Cosine would be at the digital IF carrier frequency you want to implement (1/4 of your sampling rate is often a good choice as it centers the spectrum). In any even I am going to delete my misleading answer once you had a chance to see my comment. Your question regarding how to write VHDL would not be simple enough to be answered here. $\endgroup$ Commented Nov 17, 2018 at 21:13
  • $\begingroup$ Actually I think I can update my answer to be appropriate. $\endgroup$ Commented Nov 17, 2018 at 21:14
  • $\begingroup$ There I updated my answer. I think you may benefit by first getting up to speed in wireless sytems (and FPGA coding) in smaller steps before taking this on but looks like a fun project and I wish the best to you! $\endgroup$ Commented Nov 17, 2018 at 21:23

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.