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A few months ago, as part of my summer internship, I had performed interfacing of an ADC with FPGA (Zynq-7000). The goal was to take an analog signal from a signal generator, feed it to the ADC and present the digitized output to the FPGA. The FPGA was supposed to perform FFT on the data through an algorithm which we had written on Vivado Suite. The magnitude spectrum was successfully obtained on the waveform viewer.

We then decided to calculate the SNR and SFDR values from the data. The way I proceeded for computing SFDR was to record the value of the amplitude of fundamental frequency (which kept fluctuating, but not much) and value of the next highest peak (the highest spur) in the first Nyquist zone. The ratio of these two values would fetch me the SFDR.

The input to the ADC was a 200 kHz sinewave. To check for consistency, we performed three different sized FFTs, 2k-, 8k- and 32k- and in each trial the strength of the analog signal was varied from -60 dBm to 0 dBm (in steps of 10dBm). The value of SFDR always hovered around 23 dBc.

The value of SFDR given in the ADC datasheet is around 80 to 90 dBc, but we ended up with a value much less than that (23dBc).

I understand that the conditions under which the datasheet values were calculated were quite different from ours in terms of strength and frequency of input signal.

My major concern which I wish to clarify from the experts sitting on this platform is whether or not my procedure was proper enough, or atleast worth appreciating? Was there any major flaw(s) which I may have failed to notice in my approach? I am sure there certainly were. This concern arises because whenever I think of mentioning this project in my resume, I wonder if the examiner will ridicule me of missing anything fundamental. There wasn't a subject expert at that time who could point out if I was going on the right path.

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  • $\begingroup$ what does "SFDR" stand for? $\endgroup$ – robert bristow-johnson Nov 6 '18 at 3:23
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    $\begingroup$ Spurious Free Dynamic Range $\endgroup$ – MaxFrost Nov 6 '18 at 4:14
  • $\begingroup$ i wonder how they define it. if "Spurious Free" can be well-defined, i imagine that SFDR can then be defined. $\endgroup$ – robert bristow-johnson Nov 6 '18 at 6:38
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    $\begingroup$ Analog Devices has several good white papers and discussions on SFDR and how to measure it. A google search of "Analog Devices measuring SFDR" produces some useful results $\endgroup$ – David Nov 6 '18 at 12:57
  • $\begingroup$ there is matlab instruction that does this job. I usually use that $\endgroup$ – MimSaad Nov 8 '18 at 15:47
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I would tend to believe that there is an indeed a flaw in the approach as the datasheet SFDR is achievable given the test conditions which are usually specified in the datasheet as well.

23 dB is SIGNIFICANT and I suspect your sine wave is not really a sine wave and you are seeing a harmonic (or an aliased harmonic).

Here are some possible culprits, some of which you may have ruled out already:

You did not specify what frequency the next highest peak was, but harmonics are usually excluded from SFDR. (400KHz, 600KHz, 800KHz, etc)

Did you sufficiently filter the analog signal prior to sampling? If not any higher aliases will fold into band. (Changing the sampling rate and retesting, not the FFT size, would give clues if this is occuring with such a strong spur).

Did you observe your test signal in the analog domain to see if it is cleaner than the SFDR you are trying to measure? If you did not look at this (with a spectrum analyzer for example) is possible your test signal itself has such a spur.

Similarly, did you confirm that your clock signal is cleaner than the SFDR you are trying to measure? Spurs on the clock will translate to spurs in the output signal as well.

Did you set the input signal level appropriately and is your ADC interface per the vendor's recommendations? Typically the best SFDR is when the input signal is one to two dB below full scale where clipping starts to occur, otherwise non-linearities the front-end of the ADC with start to reduce SFDR. If your input signal was too low then you will clearly not get the SFDR of the datasheet (typically the spurs stay at the same level, so you maximize SFDR with an input level as stated above).

As far as your resume, I don't think anyone will ridicule you given what you accomplished in this project, as long as you present what you did, what you think you understand from your efforts and admit openly that you still have a lot to learn and show that you are actively learning and interested (which you are by coming here!). That is probably one of the best skills someone new to the field coming out of an internship can have. I think it was a great project you got to do and would be impressed hearing more about it. At your level, if I was a hiring manager interviewing you, I would look for your interest and enthusiasm and complete honesty in what you understand and willingness / ability to learn. If you thought or acted like you knew something that you didn't really understand, that would typically come across as a big negative and a reason to move on to the next candidate for a technical position. Best to "under-promise and over-deliver" by immediately saying you are not an expert, you still have a lot to learn etc and then while you have the floor dive into what you did and what you learned and how excited you were about doing it. (My 2 cents being on both sides of that fence).

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  • $\begingroup$ Thank you so much for answering! I have realized most of the issues you mentioned concerning the input signal were not dealt with properly (or should say, not even bothered about) and that is where I must have gone wrong. Certainly sir, I've got a lot of stuff to learn and take care of while working on such projects. Thanks again for your invaluable answer! $\endgroup$ – MaxFrost Nov 5 '18 at 15:15
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    $\begingroup$ Yes and I did not mean to imply that you came across otherwise but more giving as reasons to certainly include such good work on your resume and how to deal with unconfident results $\endgroup$ – Dan Boschen Nov 5 '18 at 15:17

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