# VHDL fixed point implementation of IIR filter

I have a filter described by the following transfer function H(z):

$$H(z) = \frac{156 - 156z^{-2}}{16384 - 32443z^{-1}+16073z^{-2}}$$

How will this be implemented with the first term in the polynomium being different from 1?

Normally i would implement the filter with something like: $$y=156\cdot x-156\cdot x +32443\cdot y-16073\cdot y$$

but in this case, it is missing the term: $$-16384\cdot y$$

How may this term be inserted? I have tried just inserting it, inserting and shift the y's by 1. I just get noise doing this (looks like overflow).

It is to be implemented in VHDL on a FPGA.

• Hi! I guess you actually want to ask something about integer valued coefficients to be used in FPGA arithmetic hardware ? – Fat32 Oct 30 '18 at 17:27
• Yes, that must be it. – keffe Oct 30 '18 at 17:30
• Then so what's the question about that integer, how to scale it properly ? Please put a lot more hardware and numeric format details. – Fat32 Oct 30 '18 at 17:31
• I have scaled it by multiplying by 2^14, and bit-shifted 14 times to get my output. If i just send x to myoutput, it is fine. If i add the rest of the differnece exuation, i get noise looking like overflow. I am not sure of this is an FPGA implementation problem, or a problem with my difference equation. – keffe Oct 30 '18 at 17:35
• there's a problem withe the LCCDE. – Fat32 Oct 30 '18 at 17:36

## 1 Answer

Filter output has to be divided by the first term of denominator. In this case, division by 16384 can be effectively done by logical shift 14 bits to the right.