# How does harmonic distortion occur in ADCs?

We are currently testing an ADC at my workplace and the Total Harmonic Distortion is an important spec. It got me to thinking as to how it occurs in the first place

1) Can there be harmonic distortion if the input signal is a pure sine wave? In other words if the input is theatrically a clean sine wave , can the adc artifically introduce harmonics?

2) ive read quantisation noise can introduce or amplify harmonics of a signal. How does this happen?

Thanks!

• this is a good question for the electrical engineering stackexchage. but a quick answer is that the mapping of input voltage to output code (or number) that the ADC functionally does is not a perfect linear mapping. like if you add 1 volt to the input voltage and the ADC adds 0x0100 to the output code and then you add another 1 volt to the input voltage and the ADC responds by adding only 0x00F0 to the output code, that is nonlinear and nonlinearities create harmonic distortion. – robert bristow-johnson Sep 13 '18 at 23:41
• I assume you are not referring to clipping distortion, are you? Clipping would introduce a huge amount of harmonic content compared to deviations from linear mapping or quantizations related issues whose harmonic contribution would be typically much smaller and be relevant for high fidelity high precision apps – Fat32 Sep 13 '18 at 23:51

There are many distortion mechanisms in ADC but the most important ones are:

1. "static" distortion due to INL
2. Track-and-hold distortion

The first one is caused by the fact that the voltage-in-code-out relationship is not perfectly linear (INL/DNL).

An approximation of harmonic distortion based on DNL is given by (Lee, JSSCC 12/2017):

$$\mathrm{HD3} = -20\log\left( \frac{4}{3\sqrt{3}} \frac{2^B}{\mathrm{INL}_{\mathrm{max}}} \right)$$

The second one is caused by track nonlinearity. The sampling switch is for example a weakly nonlinear CMOS switch. Its on-resistance is given by (using the simple square law model):

$$R_{on} = \frac{1}{\mu C_{ox} \frac{W}{L} (V_{DD}-V_{in}-V_t)}$$

From which is can be seen that the resistance depends on the input signal (see for example Razavi, Data Conversion System Design, page 16).

This distortion can be approximated as

$$\mathrm{HD3} = 20\log\left(\frac{1}{4} \left(\frac{A}{V_{GS}-V_t}\right)^2 2\pi f_{in} R_{on} C \right)$$

For a simple CMOS switch this is by far the dominant distortion source and is practically overcome by using a bootstrap sampling switch. However, also this technique has limitations.