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I have optical OFDM baseband TX and RX implemented in FPGA. The design is tested using one FPGA board in loopback connection from DAC to ADC via coaxial cable. It works fine, the BER is about 1.10^-8 for QAM-16 modulation. The ADC output is captured, and looks like this: ADC output in loopback connection

When I implement the TX and RX in two board (one board for TX and another for RX), there is problem. The ADC output (captured from FPGA) looks like this: ADC output (two board)

The amplitude of the OFDM signal is reduced, so the synchronizer (using training symbol) fails to detect the start of symbol.

System specification:

  • DAC sampling rate: 50 MHz, resolution 14-bit
  • Analog LPF (after DAC): 50 MHz
  • Analog LPF (before ADC): 50 MHz
  • ADC sampling rate: 50 MHz, resolution 14-bit

Question:

  • What is the mistake in design, is it because of the ADC sampling rate, which is equal to the OFDM bandwidth?
  • When sampling OFDM signal, should I use ADC sampling rate larger than 2x bandwidth (nyquist)?
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  • $\begingroup$ Hi @Yohanes I would like to help you but I think your question is 5 levels higher than it needs to be; there would be a lot more to go through with your entire system design to know exactly what is wrong between the two plots. But sampling a 50 MHz BW signal with a 50 MHz sampling clock indicates you may benefit by reviewing sampling theory as the next step. You may also have issues with your transmitter and receiver clocks being asynchronous (not knowing if your design is doing appropriate clock recovery or not). $\endgroup$ – Dan Boschen Sep 15 '18 at 0:57
  • $\begingroup$ I recommend that you start with sampling processes to be sure you understand what sampling rate would be required, what filtering would be required etc and then ask a question specific to that (once you have studied it a bit more first) on any areas where you are still stuck. Not your specific system where we would need to go through a lot more details, but your understanding of what sampling rates are required in general. I believe you will benefit by going through that. $\endgroup$ – Dan Boschen Sep 15 '18 at 0:59
  • $\begingroup$ Hi @Dan thank you for your comments. I also think that the issue is in Tx and Rx clock being asynchronous, because I have not implemented clock recovery. $\endgroup$ – Yohanes Erwin Sep 17 '18 at 2:11
  • $\begingroup$ Yes agreed so the very short answer if you have 50 MHz of real (?) bandwidth, you should sample with at least 130 MHz or more depending on your analog filter impelmentation, allowing some spectral room for freuqency roll-off. (anything above half your sampling rate will fold into band, so if you did use 130 MHz, $f_s/2$ is 65 MHz, and therefore anything above 80 MHz will fold into the spectrum at 50 MHz and below. So this choice gives you the ability to have an analog filter that passes DC to 50 MHz and rejects above 80 MHz. There are specific design details but this gives you the general idea $\endgroup$ – Dan Boschen Sep 17 '18 at 2:17
  • $\begingroup$ I hope that is helpful $\endgroup$ – Dan Boschen Sep 17 '18 at 2:18

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