Detecting fundamental zero crossing point

I am looking for ideas from the more experienced members on algorithms for determining the fundamental zero crossing point of a 50 or 60 Hz signal. The fundamental zero crossing point is then used as the commencement point to calculate the RMS value of the original (voltage) signal AND other (current) signals.

Typically the frequency content of the Voltage is below 5% THD. At the moment I can't give u an exact figure on the SINAD but the typical Voltage signal will almost always be at 75% full scale (~250mV), or close to, of a delta sigma ADC (SINAD 110db) channel, with a sampling rate set to 6.4kHz. The target is an embedded DSP ARM M7 ~200Mhz with floating point hardware.

Ideally i would like to have 3-4 algorithms to prototype in Matlab and find the most appropriate. FIR vs. IIR vs. Bandpass vs. Zero-phase? Smarter approach? Would like to understand issues relating to sensitivity to noise, harmonics, group delay, edge effect, etc...

The IEC 61000-4-30:2015 standard on Power Quality states: "r.m.s. voltage, refreshed each half-cycle value of the r.m.s. voltage measured over 1 cycle, commencing at a fundamental zero crossing, and refreshed each half-cycle.

r.m.s. current, refreshed each half-cycle value of the r.m.s. current measured over 1 cycle, commencing at a fundamental zero crossing on an associated voltage channel, and refreshed each half-cycle."

Thanks Alex

I am not confident I have the best algorithm, but short of other suggestions I could offer you this idea:

Use an NCO (Numerically Controlled Oscillator) clocked to a known and accurate time reference to create a 50 Hz or 60 Hz reference signal, and lock the NCO to the power line signal using a Phase-Locked-Loop (PLL). The NCO will lock to the power line signal in quadrature phase with optimum noise suppression (based on the loop design and desired time averaging versus dynamic requirements). By reading the phase accumulator word the instantaneous phase offset between the power line signal and the time reference can be determined.

This idea is developed as follows:

If you have a known time reference and can generate a reference 50 Hz or 60 Hz sinusoidal signal, then you can use a phase detector (by multiplying the two signals and low pass filtering) to determine the phase difference between the two, and from the determined phase can determine the zero crossing relative to the known time reference. There will be calibration involved to offset the time delay of the low pass filtering. The advantage of this approach over single sample decision metrics (threshold zero crossing detectors) is its relatively high noise immunity based on the frequency cut-off (averaging time) of the low pass filter used. The phase detector is based on the mathematical relationship between the product of two sinusoids at the same frequency; the result is an output magnitude that is proportional to the cosine of the phase of the two signals. This provides an unambiguous mapping of phase to magnitude over a 0° to 180° range. Most significant is the result is averaged (via the low pass filter) over all samples taken, so benefits from significant noise averaging- EVERY sample in the waveform is used and contributes to the estimate of the waveform's phase position!

This is not yet complete as the primary drawback with this approach is that if the two signals approach 0° and 180° phase, the slope of the phase detector output approaches 0; meaning the result is not very sensitive (accurate) to phase shifts. The ideal operating point is when the two signals are in quadrature as the output would have the highest slope (sensitivity) to phase changes. This leads to the improved approach of using a reference signal where you can precisely control the phase, and adjust the phase to the quadrature relationship between the signals by monitoring when the output of the phase detector is zero- this is basically how many phase locked loops are designed to operate, and you could use such a phase locked loop (PLL) approach to do this adjustment automatically; as long as you have accurate knowledge of the relationship between the control to your reference waveform and its phase. Further this gives you well designed control of your averaging time via the loop bandwidth of the PLL design. A numerically controlled oscillator is such a device where you have precise knowledge of its phase at any given time, based on its phase accumulator.

For more details on the NCO implementation, see this link: Numerically Controlled Oscillator (NCO) for phasor implementation?

• Thanks for your suggestion Dan. It looks very promising as I should have reference time using PTP. Do you think that is accurate enough? I will have a look at your more detailed link soon. Sep 13 '18 at 7:17
• @almost_linear What you want to get is the TDEV and MTIE measurements for your local PTP based clock. (See this for example: community.cambiumnetworks.com/t5/PTP-Configuration-Examples/…), and this file:///C:/Users/Dan/Downloads/E70EC4FF-05F9-4976-A711226F00D349D8.pdf. The MTIE result will tell you the maximum error over a particular time interval. Of interest to how long you can average for (loop BW) and still improve accuracy/reduce noise is the TDEV. Sep 13 '18 at 11:55
• On a TDEV plot the horizontal axis refers to the averaging time (tau) and the vertical axis is the rms error between different time intervals spaced by tau. If TDEV is still decreasing as tau is increasing, then your overall variance will improve if you average over this interval. TDEV will eventually bottom out, at which point no improvement from further averaging will be gained. TDEV will then start to rise as tau increases (indicating wander or drift) and if you average for this long your performance will actually be worst! Sep 13 '18 at 11:58
• You may alternatively come across ADEV curves of your time reference; this is the same thing just in terms of frequency accuracy instead of time accuracy but gives you the same quick result of what is the optimum time to average for to maximize accuracy (if you can tolerate the averaging time for other reasons such as loop stability and response time requirements in the loop design) Sep 13 '18 at 11:59
• Thanks for the info Dan. I am not at all experienced with NCOs, PLLs or PTP but will give it a try out of need and newly created curiosity. Sep 14 '18 at 9:23