Why does Costa's loop PLL bandwidth need to be narrow? and why can't it track a certain frequency offset? and does that hold even if it has a filter with a pole at DC?

  • $\begingroup$ Please use appropriate tags! dsp-core is about digital signal processors, i.e. about the physical chips. Your questions are very broad and make assumptions that don't apply universally; the second question is based on a fallacy; the third is confusing. Maybe it would be good to explain from where you get these questions! $\endgroup$ – Marcus Müller Jul 26 '18 at 7:36

Costa's loop is related to traditional PLLs. One way of characterizing a PLL is by its loop bandwidth and damping factor. The damping factor determines the loop response (under-damped, over-damped or critically damped). The loop bandwidth determines how fast a PLL/Costas will achieve a "lock". The higher the loop bandwidth, the shorter the acquisition time. However, higher loop bandwidths result in higher tracking error (and hence higher locking threshold SNR - See graph below). Therefore, the loop bandwidth is a tradeoff between acquisition time and tracking error. In some systems, the PLL/Costas start with a higher loop bandwidth before acquisition. After acquisition, the loop bandwidth is reduced to minimize tracking error. Effect of loop bandwidth

The following terms associated with general PLL can answer your second question

  1. Pull-in range: is the maximum initial frequency difference between the input and VCO center frequencies both in positive and negative directions, for which the PLL eventually achieves the phase-locked condition. The pull-in range is related to the dynamics of the PLL
  2. Lock-in range: is the frequency range over which the PLL achieves the phase-locked condition without cycle slips

A little Googling can help you to find the specific formulas of the two terms above for the Costas Loop.




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