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Say the goal is to demodulate a "wide" signal, e.g. 300 MHz wide. An SDR is available with a maximum RX bandwidth of 150 MHz (ADC sampling freq. limitation), but it comes with 2 RX channels sharing the same clock source.

The proposed approach is connecting the same antenna to both RX chains. Ideally, they would take the same clock source, but one ADC would trigger on a rising edge and the other on the falling edge of the clock, thus effectively doubling the ADC sampling rate and allowing downstream demodulation logic to correctly demodulate a 300 MHz signal.

If this is practically doable, what are the constraints (w.r.t. SDR analogue RF frontend capabilities, compensation for loss of signal strength due to splitting it into 2 RX inputs etc.) and if not, why not?

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  • $\begingroup$ If the ADC has an antialias filter, you'll lose half the signal. If it doesn't, won't both discrete signals be hopelessly aliased? $\endgroup$ – MBaz Apr 13 '18 at 15:38
  • $\begingroup$ You label this "usrp", but then proceed to worry about bandwidths that are laughably small for that range of SDRs. So, I guess you're not actually using USRPs, or you actually have to work with much larger bandwidths. Which is it? Feasibility questions always require a very detailed background to be answerable meaningfully. $\endgroup$ – Marcus Müller Apr 14 '18 at 4:08
  • $\begingroup$ @MBaz they will be aliased. But that's not a problem: it's a polyphase decomposition of the signal and can be synthesized (trivially! What is the 2- DFT?) back into a single full-rate stream. $\endgroup$ – Marcus Müller Apr 14 '18 at 4:16
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So, while you possibly could with extensive modification to the digital logic, theoretically allow the two (dual-)ADCs of the X3x0 motherboard to be offset by half a clock cycle, that still wouldn't help you: each of two potential the UBX per motherboard has a fixed frontend bandwidth of 160 MHz, and thus if you tune them to the same center frequency, you'd still only see. ±80 MHz around that.

However, what you can do is tune them to different frequencies and get two adjacent or partly overlapping chunks of 160 MHz and combine them into a larger one.

The fact that both daughterboard LOs will be synthesized from the same reference clock will mean they will only drift very slowly (if observable at all) from each other, so that with but small tracking effort based on cross-spectrum of the overlap, you should be able to keep their phase consistent.

There's a bit of a computational problem, though: to get the full 160 MHz that one daughterboard can give you, you'd have to stream at full 200 MS/s. That makes 400MS/s of complex numbers having to go from USRP to host PC (which means you'll need dual-10 Gb/s Ethernet!) to get aligned, filtered, interpolated and combined there. I'd say that implementation of that in a real-time fashion would already be a very significant challenge, even if the signal processing turns out to be easier than I suspect.

I think the core question that you should be asking yourself is how much phase continuity and gain consistency you need at the region where the lower UBX's bandwidth gets combined with the upper one's. That will dictate the exactness of phase tracking, the length of the involved filters and thus the feasibility of it all.

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  • $\begingroup$ Thank you Marcus for a great answer: let me see if I understoood it. Can you elaborate to any degree what you meant by "extensive modification to the digital logic"? Assuming the clock trick works, if an RF daughterboard was developed for the X310 with a frontend bandwith of 300 MHz, 2 such boards could be used in the exact way I had described, i.e. the 2 RX ADC sample streams could be merged on the FPGA producing a stream which could then be demodulated as if it was produced by a single ADC? $\endgroup$ – Tomislav Nakic-Alfirevic Apr 16 '18 at 13:33
  • $\begingroup$ As for using UBX boards, yes, it occurred to me that they would have to be set to different central frequencies, but I'll have to learn more to understand all the implications. W.r.t. the quite significant 400 MS/s data stream, a lot of processing could be done on the FPGA, reducing the data throughput and processing load at the host. That said, there are a number of options to get the data across (try to squeeze the last 1% out of 2x10GbEth capacity and/or use PCIe etc.). $\endgroup$ – Tomislav Nakic-Alfirevic Apr 16 '18 at 13:33
  • $\begingroup$ the PCIe link typically has lower available bandwidth than 10 GigE, and you can bundle two 10 GigE links. So, PCIe is not the solution. And unless you do not plan to bring the unprocessed full bandwidth into your computer, I don't see a theoretically possible way of easing the bottleneck! $\endgroup$ – Marcus Müller May 15 '18 at 8:35
  • $\begingroup$ Apparently so. Sounds like at least the first demodulation steps (typically including decimation) would have to be carried out on the FPGA chip. $\endgroup$ – Tomislav Nakic-Alfirevic May 15 '18 at 9:34
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In lack of more background, I can only give a general answer:

What you describe is simply an interleaved ADC; that is a technique employed in very high-rate ADCs. And high-rate definitely is more in the range of hundreds of MHz, not a mere handful! For your proposed rates, cheap ADCs can directly sample sufficiently fast. In fact, in the context of SDR, you'll find that most ADCs used are actually doing higher rates on two simultaneously sampled channels in order to allow IQ signals to be meaningfully digitized.

So, yes, that is possible, but it's incredibly hard to do well-synchronized and balanced enough. Just get a single sufficiently fast ADC. In fact, I'm not even sure what SDR-centric ADCs you're looking at that these rates become a concern at all.

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  • $\begingroup$ Ah, Marcus, the good spirit of the Ettus world! :) Thank you for your answer. As you correctly noticed, a USRP is in question and the listed bandwidths are indeed laughable, especially for the X310 with an UBX160 card. I did not think it would be a key bit of information for this particular question, but the target bandwidths are in the 250-300 MHz range. What exactly is the problem with synchronising high-speed ADCs configured to be triggered by opposite edges of a clock? What kind of balancing are you referring to? $\endgroup$ – Tomislav Nakic-Alfirevic Apr 14 '18 at 22:59
  • $\begingroup$ So, what USRPs are we then talking about? They do have very different synchronization abilities. $\endgroup$ – Marcus Müller Apr 14 '18 at 22:59
  • $\begingroup$ Sorry, I was just updating my comment when you replied: I've specified the USRP in question. $\endgroup$ – Tomislav Nakic-Alfirevic Apr 14 '18 at 23:02
  • $\begingroup$ Thanks! I'll have to defer answering this for a couple hours, but I will, in a separate answer. $\endgroup$ – Marcus Müller Apr 14 '18 at 23:03
  • $\begingroup$ Done! Can you please also go ahead and make your question reflect what you told me in your comment rather than only the original, irrelevant numbers? $\endgroup$ – Marcus Müller Apr 15 '18 at 9:31

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