So, while you possibly could with extensive modification to the digital logic, theoretically allow the two (dual-)ADCs of the X3x0 motherboard to be offset by half a clock cycle, that still wouldn't help you: each of two potential the UBX per motherboard has a fixed frontend bandwidth of 160 MHz, and thus if you tune them to the same center frequency, you'd still only see. ±80 MHz around that.
However, what you can do is tune them to different frequencies and get two adjacent or partly overlapping chunks of 160 MHz and combine them into a larger one.
The fact that both daughterboard LOs will be synthesized from the same reference clock will mean they will only drift very slowly (if observable at all) from each other, so that with but small tracking effort based on cross-spectrum of the overlap, you should be able to keep their phase consistent.
There's a bit of a computational problem, though: to get the full 160 MHz that one daughterboard can give you, you'd have to stream at full 200 MS/s. That makes 400MS/s of complex numbers having to go from USRP to host PC (which means you'll need dual-10 Gb/s Ethernet!) to get aligned, filtered, interpolated and combined there. I'd say that implementation of that in a real-time fashion would already be a very significant challenge, even if the signal processing turns out to be easier than I suspect.
I think the core question that you should be asking yourself is how much phase continuity and gain consistency you need at the region where the lower UBX's bandwidth gets combined with the upper one's. That will dictate the exactness of phase tracking, the length of the involved filters and thus the feasibility of it all.