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I am working on making a modulator in VHDL and am implementing 8PSK. Currently, I have BPSK and QPSK looking good, and I have verified the spectrums. However, now that I am moving to 8PSK, I am stuck on how the data mux to the IQ legs should work?

Currently, my implementation is two-fold for QPSK. My first method splits the bits into the I and Q legs for even/odd bits (I am not pulse shaping, purely PCM), then I basically take this I or Q bit and xor it with the MSB of the signed DCO value, in-phase for even bits and quadrature for odd bits (I am using a digitally controlled oscillator as my carrier). The second method I have is I just generate the symbols for QPSK and feed my DCO with a phase shift at 45, 135, 225, and 315 (this saves logic as I only have to use 1 DCO). I know I can use the phase request for 8PSK as well, however, this method produces a lot of spurs.

If I want to perform the following block diagram for 8PSK, how does this work? Am I accumulating 3 bits, or one symbol, for each leg, and performing a phase shift? I'm really struggling to figure out how to do this. I know I can just accumulate one symbol and send a phase shift to the DCO, but this doesn't use I and Q and feels like a crappy way of doing this, especially considering it doesn't work well when I tried it for QPSK. Here is the fundamental question, when I go from serial to parallel through the data MUX, what exactly is going onto the I and the Q leg? If it is still 1 bit, how is this any different than QPSK? enter image description here

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You are mapping a group of 3 bits (an 8PSK symbol) to one of 8 coordinates in the I-Q plane. I'm not an FPGA guy, but you can do this with a "switch" statement or a lookup table. I don't know your particular mapping, but a straightforward mapping from bits to I & Q values would be:

$$(0,0,0) \rightarrow (1, 0)$$ $$(0,0,1) \rightarrow (1/\sqrt{2},1/\sqrt{2})$$ $$(0,1,0) \rightarrow (0, 1)$$ $$(0,1,1) \rightarrow (-1/\sqrt{2},1/\sqrt{2})$$ $$(1,0,0) \rightarrow (-1, 0)$$ $$(1,0,1) \rightarrow (-1/\sqrt{2},-1/\sqrt{2})$$ $$(1,1,0) \rightarrow (0, -1)$$ $$(1,1,1) \rightarrow (1/\sqrt{2},-1/\sqrt{2})$$

Note that, in the above mapping, if you take entries 2, 4, 6, and 8, and ignore the least significant bit, you get a mapping for QPSK.

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  • $\begingroup$ No worries! I can take care of translating it to hardware, I was just stuck on what exactly I was doing. With QPSK, I was easily able to map this process to emulate the I and Q legs, but wasn't sure about if this was possible for 8PSK. I guess I will hunt down why my direct IQ mapping wasn't working for QPSK and fix that. Thank you for the response! $\endgroup$ – nichollsg Mar 30 '18 at 23:38
  • $\begingroup$ Using the phase mapping method of the symbols, how would you pulse shape this? $\endgroup$ – nichollsg Mar 31 '18 at 0:03
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    $\begingroup$ Just pulse-shape the I and Q symbols separately. $\endgroup$ – MBaz Mar 31 '18 at 0:20
  • $\begingroup$ @MBaz I understand that, but how would I go about it for 8PSK? Considering my method is passing a phase shift to my DCO, I don't have separate I and Q bits to pulse shape. Is it possible to do the shaping after the IQ "merge"? $\endgroup$ – nichollsg Mar 31 '18 at 2:47
  • $\begingroup$ Usually pulse shaping is done before the DCO. Say you want to transmit bits (1,1,1). Then $I(t) = p(t)/\sqrt{2}$ and $Q(t) = -p(t)/\sqrt{2}$, where $p(t)$ is your pulse shape. $\endgroup$ – MBaz Mar 31 '18 at 15:05
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As an alternative to the accepted answer, consider the Gray code mapping for the tribit $b_Ib_Qb_Z \in \{0,1\}^3$

\begin{align} b_I b_Q b_Z\\ 0~~0~~0~ &\rightarrow \Big(1,\qquad 0\Big)\\ 0~~0~~1~ &\rightarrow \Big(\frac{1}{\sqrt{2}},\frac{1}{\sqrt{2}}\Big)\\ 0~~1~~1~ &\rightarrow \Big(0,\qquad 1\Big)\\ 0~~1~~0~ &\rightarrow \Big(\frac{-1}{\sqrt{2}},\frac{1}{\sqrt{2}}\Big)\\ 1~~1~~0~ &\rightarrow \Big(-1,\quad 0\Big)\\ 1~~1~~1~ &\rightarrow \Big(\frac{-1}{\sqrt{2}},\frac{-1}{\sqrt{2}}\Big)\\ 1~~0~~1~ &\rightarrow \Big(0,\quad~ -1\Big)\\ 1~~0~~0~ &\rightarrow \Big(\frac{1}{\sqrt{2}},-\frac{1}{\sqrt{2}}\Big) \end{align} which puts complementary bit patterns at diametrically opposite constellation points and forces nearest neighbor constellation points to have bit patterns differing in only one place.

If we look at alternate bit patterns going around the circle, then

  • 001, 101, 111, 100 map to a standard QPSK signal constellation corresponding to the two leftmost bits $b_I,b_Q \in \{0,1\}$ being applied to a standard QPSK modulator and resulting in the signal \begin{align} s(t) &= \left.\left.\frac{1}{\sqrt{2}}\right[(-1)^{b_I}\cos(2\pi f_c t) - (-1)^{b_Q}\sin(2\pi f_c t)\right]\tag{1} \end{align} The least significant bit $b_Z \in \{0,1\}$ is "ignored", but see below.

  • 000, 011, 110, 101 also correspond to a QPSK constellation with data bits $b_I$ and $b_Q$, albeit one that is rotated by $45^{\circ}$ clockwise, or, effectively, with the inphase and quadrature carriers are delayed by $\pi/4$ radians. The signal now is \begin{align} s(t) &= \left.\left.\frac{1}{\sqrt{2}}\right[(-1)^{b_I}\cos(2\pi f_c t-\pi/4) - (-1)^{b_Q}\sin(2\pi f_c t-\pi/4)\right]\\ &= \left(\frac{(-1)^{b_I}+(-1)^{b_Q}}{2}\right)\cos(2\pi f_c t) - \left(\frac{-(-1)^{b_I}+(-1)^{b_Q}}{2}\right)\sin(2\pi f_c t)\tag{2} \end{align} which also seemingly ignores $b_Z$. Note that the quantities in large parentheses in $(2)$ can take on values $0$ and $\pm 1$ and $(2)$ reduces to one of $\pm\cos(2\pi f_ct)$ and $\pm\sin(2\pi f_ct)$ corresponding to $(1,0), (0,1), (-1,0), (0,-1)$ in the 8PSK constellation diagram.

So, how do we know whether the 8PSK modulator output should be $(1)$ or $(2)$? Well, that's where the value of $b_Z$ comes in. The 8PSK modulator output should be

\begin{align} s(t) &= \begin{cases}\left.\left.\frac{1}{\sqrt{2}}\right[(-1)^{b_I}\cos(2\pi f_c t) - (-1)^{b_Q}\sin(2\pi f_c t)\right], &\text{if}~ b_I\oplus b_Q\oplus b_Z = 1,\\ \left(\frac{(-1)^{b_I}+(-1)^{b_Q}}{2}\right)\cos(2\pi f_c t) - \left(\frac{-(-1)^{b_I}+(-1)^{b_Q}}{2}\right)\sin(2\pi f_c t)&\text{if}~ b_I\oplus b_Q\oplus b_Z = 0,\end{cases} \end{align}


Some further thoughts: If the input to the 8PSK modulator is at rate $R$ bps (bit period $T = R^{-1}$ seconds), then the serial input is converted to tribits $(b_I, b_Q, b_Z)$ in a 3-bit serial to parallel converter. $b_I$ and $b_Q$ are used for modulation onto $I$ and $Q$ carriers but note that these modulate the carriers for all of $3T$ seconds by which time the next tribit has been converted from serial to parallel. So it is not quite the $R/2$ marked on the OP's diagram for 4PSK. And, as noted above, $b_Z$ is used in determining whether $(1)$ or $(2)$ is to be used in creating the signal.

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  • $\begingroup$ So does this essentially combine normal QPSK and pi/4-QPSK where the pi/4 select is based on the bZ bit? $\endgroup$ – nichollsg Mar 31 '18 at 20:45

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