0
$\begingroup$

I am trying to implement a FIR filter on FPGA and trying to have a solid understanding of the FIR filter tap delay and sampling frequency.

Does the “one tap” delay equal to “1/Fs (sampling frequency)”? If I have N-tap, the total delay will be N/Fs? If the Fs sampling frequency is increased, the “one tap” delay is decreased?

Is there any trade off/drawback of increasing the sampling frequency? Maybe it will take more processing time for the output y(n) to come out?

Thanks

$\endgroup$
1
$\begingroup$

Does the “one tap” delay equal to “1/Fs (sampling frequency)”?

Yes

If I have N-tap, the total delay will be N/Fs?

Depends on how you define "total" delay, but in general the answer is no. For a minimum phase filter the delay will be 1. For a linear phase filter it would roughly be N/2

If the Fs sampling frequency is increased, the “one tap” delay is decreased?

Yes. But it also changes the frequency response of your filter.

Is there any trade off/drawback of increasing the sampling frequency?

Many. It really depends on what the requirements of your application are.

| improve this answer | |
$\endgroup$
  • $\begingroup$ Hello, Sir. Thank you very much for the reply. For the last question “what is the trade-off/drawback of increasing the sampling frequency”, maybe can you give me a couple potential trade-off/drawback? The only one that I can think of now is that “in FPGA implementation, the z delay is using a D flip flop, and higher Fs will mean that the D flip flop needs be have a shorter “D to Q delay (shorter delay is a little more challenging for hardware). Thank you. $\endgroup$ – Charlie Feb 1 '18 at 18:18

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.