I am trying to implement a FIR filter on FPGA and trying to have a solid understanding of the FIR filter tap delay and sampling frequency.
Does the “one tap” delay equal to “1/Fs (sampling frequency)”? If I have N-tap, the total delay will be N/Fs? If the Fs sampling frequency is increased, the “one tap” delay is decreased?
Is there any trade off/drawback of increasing the sampling frequency? Maybe it will take more processing time for the output y(n) to come out?