I need to make in FPGA (using Verilog) an FFT. Input data is N=8192 points at 1 GSPS. However, the FPGA operates at 125 MHz, therefore the data is split into 8 channels (each one at 125 MHz). This splitting of data and computing the N/8 FFT is not problematic for me, it is already done.
What I don't understand is how to combine the outputs of the N/8 FFTs to create one N FFT. I have created a schematic showing the flow of data, where blue blocks represent what is done and green blocks represent what I don't understand.
I understand generally the Cooley-Tukey FFT algorithm and Butterfly diagrams as they relate to 8 point or 16 point data, but I don't understand how these can be expanded to a 8192 input sequence.
Any help regarding the theory, math, or FPGA implementation behind how the green blocks are implemented is greatly appreciated!