Sampling at a higher rate will distribute the quantization noise over a wider frequency, thus reducing the noise spectral density due to that quantization noise, with a lot of caveats. For more details on that see
What are advantages of having higher sampling rate of a signal?
In your last paragraph, if you are referring to running the same filter at a lower rate versus a higher rate, at a lower sampling rate the digital filter will require LESS taps for the same filter performance. For more details on that see Filter Order Rule of Thumb and How many taps does an FIR filter need?.
An effective strategy to consider is to use a higher sampling rate which relaxes the analog filtering requirements and can give you more effective bits if needed at the analog to digital boundary (which are realized after subsequent filtering digitally). This is then followed by efficient resampling techniques in the digital domain to get to a lower sampling frequency prior to providing the final filtering as required in your system design (coarse and simpler filters are done at the higher rate, and then final "shaping filters" are done at the lowest rate possible thus minimizing number of taps, power dissipation and resources).
For a further details on decimating to a lower rate for improved filter performance see Fast Integer 8 Hz 2nd Order LP for Microcontroller.