According to the 6dB-per-bit rule, a 16-bit DSP would provide 96 dB of dynamic range, approximately.

If the ADC and DAC are both 12-bit long, the DSP is still considered to have 96 dB, or the dynamic range is now 72 dB?

Also, I would like to know if the guard bits provided by the accumulator (40-bit) increase in some way the dynamic range.

Thank you very much.

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    $\begingroup$ Not the DSP would have that the dynamic range, the 16bit variables that it can natively handle would. Notice that a "16bit DSP" usually means that the address space is 16 bit, not that the native numerical format necessarily is 16 bit. $\endgroup$ Jun 6, 2017 at 11:49
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    $\begingroup$ Exactly as @MarcusMüller said, it depends on the for numerical format, whether it is float or fixed point does matter. Anyway, since the whole procedure of process of the signal is serial (ADC -> DSP -> DAC), the dynamic range is dominated by the least accurate component $\endgroup$
    – MimSaad
    Jun 6, 2017 at 12:49
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    $\begingroup$ You are limited by the dynamic range of the ADC which is most likely less than the 12 bits it provides (see its ENOB). Yes the accumulator can allow for increasing dynamic range to the internal datapath precision of the DSP; effectively through oversamplling and subsequent filtering- however there are a lot of challenges and hurdles to overcome such as possible in-band spurs from the ADC that can limit your dynamic range. $\endgroup$ Jun 6, 2017 at 14:29
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    $\begingroup$ i have to downvote what @MarcusMüller wrote. whether it's a DSP or a CPU or an MCU or whatever they wanna call it, to call something an "N-bit chip", means that the data bus is N bits wide. an 8-bit microcontroller has an 8 bit wide data bus and a 16-bit DSP has a 16 bit wide data bus. and normally, the fixed-point word that is most "native" to that chip is the same width as the data bus. so i would expect the natural word size to be 16 bits. that doesn't mean the chip doesn't support words of double width. $\endgroup$ Jun 6, 2017 at 16:07
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    $\begingroup$ @robertbristow-johnson who am I to argue with you on DSPs :) let's focus on the issue at hand, though: the DR is defined by how you handle the data, not by the DSP's bittiness alone. $\endgroup$ Jun 6, 2017 at 17:23

2 Answers 2


The dynamic range is the ratio between maximum and minimum representable values. It is $DR = max/min$. So:

  1. For an ADC and its configuration (Vref, uniform step, ENOB, etc...), as you said, $DR = 6 \cdot N $, where $N$ is the ENOB of the ADC. However, you can vary the configuration of the ADC stage to adapt it to your signal. So, at each moment, an ADC can have different $min$, $max$ or $DR$ by changing its configuration (in real-time or off-line) at the expense of other metrics (quantization noise mainly). For example, if you have an ADC that does not perform an uniform quantization, you could increase the DR. The reason why uniform quantization is the most common among ADCs is because no statistics about the signal to be sampled is available to the ADC designer, for some signals, however, uniform quantization is not the best.

  2. A DSP can perform arbitrarily high dynamic range operations with proper software the same way it is possible to perform 1024-bit arithmetic in a 32-bit register machine. Even if the ADC data has DR=96dB, internally, the DSP can raise that DR as much as resources it has. For example, if two number with DN=96dB are multiplied, you get a result with DR=192dB as long as you store all the result bits. If your accumulator cannot handle such number of bits, you can always make arithmetic transformations over your computation not to saturate the accumulator.

  3. The guard bits in the accumulator helps not to make those arithmetic transformations for reasonable DRs along the data flow (intermediate results) of the algorithm.

So, to answer to your only question: the DR of a DSP is arbitrary (only constrained by software algorithms, memory to store the programs, real-time constraints...), with the information you provide is not possible to give an answer. On the other hand, a 12-bit ADC has not necessarily a DR=72dB, but for the vast majority of ADCs out there (uniform quantization) it is like that.


Let me add the following additional important consideration to dynamic range on the ADC side of the equation to the other answer provided.

The SNR as characterized with a full scale sine wave for a typical (uniform quantization noise) ADC is well established to be given by the following relationship:

$$SNR = 6.02 dB/bit + 1.76 dB + 10 Log(N)$$

(For more on how that equation is derived, see What are advantages of having higher sampling rate of a signal?)

Which demonstrates the consideration given for oversampling to dynamic range. (And just to mention, there are other ADC typologies such as Delta-Sigma with noise shaping offering even more dynamic range improvement due to oversampling; however in any case the sampling and the distribution of the quantization noise is limited to the architectural implementation of the ADC itself).

The example below illustrates this with a 10 MHz BW signal at a digital IF of 25 MHz, sampled at 100 Msps. This example was done with Analog Devices HMCAD1520 which is a 14 bit ADC with a SINAD (Signal to Noise and Distortion) of 72.5 dB. 72.5 dB translates to an ENOB (Effective Number of Bits) of 11.8 (using the same 6dB/bit+1.76 dB equation). This means that with a full scale sine-wave, the additive noise due to the ADC sampling process will be 72.5 dB lower than the power level of the sine-wave itself. However this noise, well approximated as a white noise source is spread evenly across the sampling spectrum. Thus as shown in the figure below, the portion of the noise that is within the bandwidth of the signal is 1/5 or -7 dB lower.

The rest of the noise, out of the band of interest, can be filtered out in the DSP, down to the limits of the datapath (unless special provisions are made to effectively increase the datapath precision as suggested in the other answer). For this filtering purpose, extended precision accumulators are particularly important, as described in more detail in other posts. (for example, see what is the suitable design Method to the filter?)

Some of the distortion is in spurious frequencies, but referring to the datasheet for this device, the SFDR (Spurious Free Dynamic Range) is 83 dB, so in this specific case, with this oversampling rate, the dynamic range will not be limited by spurs.

ADC Noise Floor

So given a sine wave at full scale (to establish a consistent metric point), we can establish the ADC noise floor. However for dynamic range, we also need to consider the headroom required for a modulated signal. For this reason I have created the following graph which is applicable to Gaussian distributed waveforms in magnitude (such as OFDM and CDMA both of which are well approximated by Gaussian distributions), and shows the optimum set point in rms level below full scale in order to maximize dynamic range for the case of a modulated waveform based on the number of bits. This is applicable throughout the digital system everywhere in the datapath, not just at the ADC, so is a very important consideration. This shows specifically the effect of clipping noise as the rms signal level approaches full scale, and the effect of quantization noise increasing relative to the signal, as the rms signal level is reduced from full scale. The term "dBFS DC" is the level in dB below full scale of a DC signal (a sine wave at "0 dBFS" is -3dB below '0 dBFS DC"). The 0 dBFS DC mark is also applicable to full scale for a single tone in a complex datapath (with I and Q).

Max ADC Input Signal


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