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I am currently using a combination of 4 ADSP 21469 because of the complexity and huge chunk of code that I currently have. BOOT and application will execute from external Flash memory. The code for radar processing are equally distributed across 4 DSPs

Even after splitting the code across 4 DSPs, I still need to perform code optimization because of memory constraint. By doing a certain level of optimization, my variables are not accessible due to which I have to read from the registers, which vary all the time.

My thought was to use a single advanced processor that is robust enough to contain all the code so I can use common libraries wherever I can to make my code efficient on target.

To summarize, the bottleneck is that ADSP 21469 has 5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM which is way less than my requirement. If I can use a multicore processor(Ex:quad code) that works at >=400 Mhz, which has an on-chip memory of >=20 Mb to hold all my data fr a faster access or supporting external memory without being slower in accessing the data.

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  • $\begingroup$ pretty much impossible to help you here without knowing what you're doing on these 4 DSPs, and where exactly your bottleneck lies, and what hardware interfaces you need etc. $\endgroup$ – Marcus Müller May 18 '17 at 13:33
  • $\begingroup$ I removed the unrelated tags; you have the radar(radar) tag; does that mean you do radar? What kind of radar? which data rates? Which processing steps? $\endgroup$ – Marcus Müller May 18 '17 at 13:34
  • $\begingroup$ I have split the code for Radar Signal Processing into 4 DSPs allocating different functions for each DSPs, with this, it has crossed my memory constraints. The ADSP 21469 has only 5Mb of RAM and 4Mb of ROM. I have used the bootload onto ROM and using a Flash to dataload the RAM memory with the code in each of the 4 DSPs. Now, I am trying to find a DSP that has more on-chip memory so I dont have to split the code. $\endgroup$ – Ram May 18 '17 at 13:42
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    $\begingroup$ You'll need to describe your whole radar processing chain – it's really impossible to guess what your system needs to fulfill without knowing what it'll be used for. $\endgroup$ – Marcus Müller May 18 '17 at 13:44
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    $\begingroup$ Notice that someone (not me, so far) voted to close the question as purely opinion-based – and they're right! You don't explain what you technically need to achieve, but only ask for a "better" (whatever "better" is) device. That's like 3rd graders comparing who's got the best car – certainly, a high-end Ferrari has more horse powers than the average garbage truck, but have you ever tried transporting 5 metric tons of garbage in a sports car? $\endgroup$ – Marcus Müller May 18 '17 at 13:46
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That depends a bit on the constraints: are you out of code space or data space or both?

Anyway, the typical way of dealing with space problems is to use external memory in conjunction with a fast access internal cache. An alternative would be something like this http://www.ti.com/lsds/ti/processors/dsp/c6000_dsp/c66x/overview.page with a few gigs of DDR attached.

Obviously external memory is somewhat slower than internal memory, so the trick is to move data efficiently into internal memory, so that it's there when you need it. In many cases the processor will do a pretty decent job in managing this automatically, especially if it's mostly code (not data) and most MIPS consumption is in loops.

If that's not good enough, there are certainly strategies to manually optimize code for cache efficiency as well.

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  • $\begingroup$ Hi Sir, I looked at ti.com/lsds/ti/processors/dsp/c6000_dsp/c66x/overview.page. I would like to know the performance of 450MHz processor with internal memory vs 1.4GHz Quad Core processor with an external memory. Also, I was thinking of a Quad Core processor as I am replacing 4 existing processors. Please let me know your thoughts on this. $\endgroup$ – Ram May 21 '17 at 8:03
  • $\begingroup$ If you could please let me know if there are any simulators that are available to check this before I go for a hardware-respin to check the design.This would improve both size and performance of my hardware and software significantly. $\endgroup$ – Ram May 21 '17 at 8:04
  • $\begingroup$ I suggest getting an evaluation with Code Composer Studio from TI. Cache performance is very hard to simulate. $\endgroup$ – Hilmar May 22 '17 at 11:35

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