Transfer function of a PLL Loop Filter that can support a linearly increasing (chirping) frequency

Question

What is a transfer function for a the loop filter of a PLL that can track a sinusoid of the form:

\begin{equation} x(t)=\cos\left(2\pi\left(\frac{1}{2}c_0t^2 + f_0t + \phi_0\right)\right) \end{equation} where $c_0$ is the chirp (units of Hz/s), $f_0$ is the center frequency (units of Hz) and $\phi_0$ (units of cycles) is the initial phase?

I am currently using a loop filter followed by a direct digital synthesize (DDS). The loop filter I am currently using is a proportional plus integrator loop filter with transfer function \begin{equation} F_{\text{loop}}(z) = k_1 + \frac{k_2}{1-z^{-1}}. \end{equation} The DDS has a transfer function of \begin{equation} F_{\text{DDS}}(z) = k_0\frac{z^{-1}}{1-z^{-1}}. \end{equation}

I would like to replace the loop filter with one that, combined with the DDS, can track the aforementioned sinusoid. The feedback loop is configured in the usual manner, namely, conjugate-multiplying the output of the DDS with the input sinusoid and then the output of that is fed into the loop filter, and, finally, the output of the loop filter is fed into the DDS. (Sorry I don't have a block diagram.)

This PLL works well with no noise present and $f_0 < 10$ and so, is clearly not very useful. I need something that can handle a phase offset, a phase ramp (nonzero frequency), and a frequency ramp (nonzero chirp) simultaneously, in addition to some noise.

NOTE: I have simplified this down to tracking a sinusoid. I'm actually tracking the phase of a modulated signal and so, rather than conjugate multiplying, I feed the match filter and the DDS outputs into a phase error detection function. However, for my purposes here, this simplified approach should suffice.

(I thought about posting this to the Electrical Engineering stack exchange, but since I'm working with a completely digital implementation, my question felt more natural here.)

Answer 1

To track a frequency ramp with a Phase lock loop, with zero steady state error requires a type 3 PLL Loop; which means three integrations (DC Poles) in the open loop gain (your NCO would be one of the integrators and your loop filter needs to provide the other two). Stabilizing such a system becomes more challenging but here is one reference paper detailing an approach to the design:

http://vbn.aau.dk/files/72548181/Final_PLL.pdf

This picture helps clarify tracking and loop order; given a phase lock loop, phase is the parameter being tracked. A frequency ramp as you are dealing with is an accelerating phase, hence the requirement for a type 3 loop. The detailed loop filter design would depend on your overall system and related gain coefficients for your specific design, but I hope the above reference offers some guidance to help you.

Also note that many people often confuse "Type" with "Order", so to be very clear a Type Three Loop is not the same as a Third Order Loop. Specifically a Type Three Loop must be Third Order (or higher), but a Third Order Loop need not be Type 3. Type specifically is number of integrators in the loop, which are poles at z=1 in the open loop gain, while order is the total number of poles, regardless of location (specifically the order of the denominator polynomial of the open loop gain, which ends up being the order of the closed loop gain given proper transfer functions).