There can be several reasons.
One reason to use IQ data for SDR processing is to lower the computational processing rate (to use a slower or lower power processor) for visualization (panadapter) or demodulation without an additional conversion step. Many modulation schemes have asymmetric sidebands. IQ signals can carry disambiguated information about both sidebands around DC (0 Hz) (see explanation here), which means the processing rate can be very close to DC (0 Hz + signal bandwidth + filtering transition safety margin), as opposed to above twice the carrier frequency (plus signal bandwidth, filter transition band, and etc.). In fact, some SDR modules (Funcube Dongle Pro+, Elecraft KX3, etc.) produce IQ data into a PC stereo audio interface (thus allowing processing at very low audio data rates compared to much higher VHF/HF RF carrier or HF/LF IF frequencies).
To do processing with a single channel data stream requires either a very high processing rate (above 2X the RF carrier, using an FPGA, etc.), or some way to get rid of images or aliasing before downsampling/downconversion, usually by an additional conversion or mixing step (or more) to an IF frequency, plus one or more associated anti-aliasing filters for image rejection. Thus, a 2X rate single real data stream usually requires an additional IF stage (and/or a very narrow high frequency bandpass filter, often crystal or SAW) to do this compared to producing a 1X rate IQ data stream. An additional IF stage usually requires an additional oscillator and mixer as well. Whereas direct conversion to IQ data can be accomplished without the need for a high frequency band-pass or roofing filter for image rejection. And even double conversion to IQ data using an IF (intermediate frequency) often requires one less filter or one much lower quality filter (again, for equivalent image rejection).
The downconversion oscillator can be centered (or nearly so) on the signal carrier of interest (either RF or IF), or a low multiple, instead of being either offset or much higher. This can make tracking, phase locking, or synchronizing this oscillator simpler, and thus allow the frequency readout and/or transceiver transmitter signal generation to be simpler in minimal radio hardware.
In hardware, it may be easier or cheaper to implement 2 ADCs at a lower sample rate, than 1 ADC at a higher sample rate. For instance, you can use a stereo sound card with a 44.1k (or 192k) sample rate, instead of a more expensive sound card with a 96k (or 384k) sample rate, for nearly the same signal bandwidth capability.
IQ sample streams (created by two channels of 90 degree phase shifted mixing and/or sampling) also correspond closely to mathematical complex signals (with real and imaginary components), which makes it easier to think of the two channels of real data as one channel of a complex mathematical representation. This makes certain mathematical algorithms (DFT/FFT, complex envelope demodulation, etc.) more directly applicable (and, as mentioned above, at baseband processing rates) with less additional mathematical operations (offsets or fftshifts, etc.)
An explanation or description of these DSP algorithms using complex math usually requires less writing on a classroom chalkboard than equivalent explanations using a non-complex higher sample rate representation (as well as being far more elegant in the opinion of many.) These simpler complex/IQ explanations sometimes directly translate to less code (depending on the HLL computer language at its supported data types), or less computational blocks (using a graphical signal path design tool) is SDR applications.
The downside, of course, is the need for accurate 90 degree phase shift generation, 2 ADCs instead of one, and complex multiplications (4X hardware multipliers or instruction OPs) instead of a single multiplications per (real or IQ) sample, for similar operations.