a Digital Signal Processor is one that has, in its instruction set, some instructions and addressing modes that are optimized for processing digital signals.
usually these optimizations can be shown around what is needed to perform the dot-product needed for an FIR filter.
$$ y[n] = \sum\limits_{i=0}^{L-1} h[i]\,x[n-i] $$
to do this in, say, $L$ instructions, a DSP must be able to do in one instruction:
- multiply $h[i]$ and $x[n-i]$ together.
- accumulate that product into an existing sum.
- fetch the next $h[i+1]$ and $x[n-i-1]$ in anticipation of the next multiply-accumulate. since these are two numbers to fetch, a DSP will use something called a Harvard architecture that has at least two separate memory spaces for $h[i]$ and $x[n]$ so the DSP can fetch these two numbers simultaneously.
- addressing $x[n]$ must be in a circular queue. a DSP will perform the modulo (or "wrap around") arithmetic on the index or address of $x[n]$ necessary without additional instructions.
- the result $y[n]$ will eventually go to an output DAC or fixed-point stream and there is some way to saturate the value of $y[n]$ against some $\pm$ maximum without additional instructions. if the DSP is a fixed-point DSP, then this accumulator register will have width in bits that is the sum of the bitwidth for $h[i]$ and the bitwidth for $x[n]$ plus a few more bits on the left as "guard bits".
a general purpose CPU can do all of these, but not likely in a single instruction cycle and things like modulo arithmetic and saturation will need their own specific instructions in a general-purpose CPU.
a DSP may also have some instructions and an addressing mode that facilitates the operations of the Fast Fourier Transform (FFT). this may include instructions necessary to perform an FFT "butterfly" in as few as four instruction cycles (or two instruction cycles if SIMD is operational).